CY8C5368AXI-106 Cypress Semiconductor Corp, CY8C5368AXI-106 Datasheet - Page 8

• Manufacturer Part Number: CY8C5368AXI-106
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5368AXI-106

• Lead Free Status / Rohs Status: Compliant

Figure 2-3
analog performance on a 2-layer board.
For information on circuit board layout issues for mixed signals, refer to the application note
Layout Considerations for PSoC® 3 and PSoC 5.
Note The two V
shown in
Document Number: 001-66237 Rev. *A
The two pins labeled V
The two pins labeled V
page 22. The trace between the two V
The two pins labeled V
Vssd
Figure
and
Figure 2-4
CCD
2-4.
pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
Vssd
Figure 2-3. Example Schematic for 100-Pin TQFP Part with Power Connections
DDD
CCD
SSD
on page 9 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal
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11
12
13
14
15
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17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Vddd
Vssd
must be connected together.
must be connected together.
must be connected together, with capacitance added, as shown in
0.1 uF
0.1 uF
C6
C12
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWDIO
P1[1], SWDCK
P1[2]
P1[3], SWV
P1[4]
P1[5]
Vddd
Vssd
CCD
pins should be as short as possible.
PRELIMINARY
Vddd
Vssd
0.1 uF
C16
1 uF
C1
Vssd
Vddd
0.1 uF
C2
Vssd
1 uF
C15
PSoC
Vccd
Vssa
10 uF, 6.3 V
OA0-, REF0, P0[3]
C13
kHzXout, P15[2]
®
kHzXin, P15[3]
OA0out, P0[1]
OA2out, P0[0]
OA3out, P3[7]
OA1out, P3[6]
OA0+, P0[2]
5: CY8C53 Family Datasheet
SIO, P12[3]
SIO, P12[2]
SIO, P12[1]
SIO, P12[0]
Vssa
Vddio0
0.1 uF
C14
U2
CY8C55xx
P4[1]
P4[0]
Vdda
Vssd
Vssa
Vcca
NC
NC
NC
NC
NC
NC
AN57821 - Mixed Signal Circuit Board
Vddd
Vssd
Figure 2-3
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58
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53
52
51
C11
0.1 uF
Vssd
Vssa
Vcca
Vdda
Vddd
Vssd
0.1 uF
C8
and
C9
1 uF
Vssa
Vssd
Power System
Vdda
Vssa
Vdda
Page 8 of 106
1 uF
0.1 uF
C17
C10
on
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