NOIL1SE3000A-GDC ON Semiconductor, NOIL1SE3000A-GDC Datasheet - Page 12

• Manufacturer Part Number: NOIL1SE3000A-GDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SE3000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Protocol Layer
layer before it is transferred to the LVDS drivers. Perform
these operations in the protocol layer:
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•
•
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Table 11. AFE AND ADC PARAMETERS
Total AFE + ADC latency
Total AFE + ADC power
(32 channels = 64 AFE + ADC)
Digital data from the ADCs is reorganized in the protocol
Multiplexing of two ADCs to one output data channel.
Adding the cyclical redundancy check (CRC)
checksum to the data stream. This operation is done
row by row. A new CRC checksum is calculated for
every new row that is readout.
Switching readout mode. The LUPA3000 sensor is
programmed to operate in two other readout modes:
training and test image modes. These modes
synchronize the readout circuitry of the end user with
the sensor.
Assembling the data stream of the synchronization
channel.
(msb first)
datain
Parameter
lsb
x0
Figure 11. Equivalent Polynomial Representation in Serial Format
x1
44 master clocks
400 mW (at 2.5 V)
Parameter Value (typical)
x2
http://onsemi.com
x
8
+ x
x3
12
6
+ x
CRC
processed data to detect errors during the high speed
transmission. CRC provides error detection capability at
low cost and overhead.
x^8+x^6+x^3+x^2+1.
When the data is received (or recovered), the CRC algorithm
is reapplied and the latest result compared to the original
result. If a transmission error occurs, a different CRC result
is obtained. The system then chooses to operate on the
detected error or has the frame resent.
to improve bit error detection efficiency.
each row and inserted into the serial data stream. Bit 0 of SPI
register 71 (decimal) is an enable bit to insert the CRC
checksum. CRC is enabled when a logic 1 is written to this
bit. This is the default (POR) value. Bit 1 of this register
allows calculation and insertion of a CRC checksum to the
“synchronization” channel. No checksum is attached by
default.
3
LUPA3000 implements a CRC for each row (line) of
The CRC polynomial implemented for LUPA3000 is:
The CRC result is transmitted with the original data.
The CRC shift register is initialized with logic 1s at reset
Referring to Figure 11, the CRC value is calculated for
+ x
x4
2
5.5 ADC clocks = 1/8 of master clk
160 mA
+ 1
x5
Comment
x6
msb
x7