NOIL1SE3000A-GDC ON Semiconductor, NOIL1SE3000A-GDC Datasheet - Page 17

• Manufacturer Part Number: NOIL1SE3000A-GDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SE3000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

On−Chip BandGap Reference and Current Biasing
for the AFEs, ADCs, and LVDS I/O, LUPA3000 includes a
bandgap voltage reference that is typically 1.25 V. This
reference is used to generate the differential Vrefp–Vrefm
ADC reference and a analog voltage reference for the LVDS
driver I/O.
reference for the LVDS drivers and bias currents for all of the
analog amplifiers. A Current-Ref_2 pin is included on the
package to allow connection of an ~50 K resistor (±1%) to
gnd to realize a desired 25 A current sourced from the
LUPA3000 device. A buffered version of the internal
bandgap reference is monitored at this pin.
bandgap regulator. Control bits in SPI register 74 (decimal)
allow this feature. Bit 2 is a power-down control bit for the
internal bandgap. Setting this bit high along with bit 1
(int_res), and bit 0 (bg_disable), allow driving the
Current_Ref_2 pin with an external reference. An internal
current reference resistor of 50 K to ground is applied. This
mode has reduced current accuracy; ~±10% from the
external resistor mode (±1%).
available through bits 2:0 of SPI register 64 (decimal). This
Table 14. REFERENCE AND BIAS PARAMETERS
Vrefp
Vrefm
Vrefp–Vrefm
Vcm
Current_Ref_2
Bandgap reference (internal)
For current biasing and voltage reference requirements
The bandgap reference voltage also forms a stable current
An optional mode is available to enable an external
Five trimming levels for the internal bandgap voltage are
Parameter
1.7 V to 1.75 V
0.8 V to 0.75 V
0.95 V to 1.0 V (difference)
0.9 V
1.25 V ± 0.1 V at 25 mA to gnd
1.25 V ± 0.05 V at 2.5 V, T = 40°C
Parameter Value (Typical)
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allows minor adjustment in process variations for voltage
level and temperature tracking. A POR value is preset so that
user adjustment is not required. Each setting adjusts an
internal resistor value used to adjust the PTAT (proportional
to absolute temperature) “K” factor ratio. Each of the five
settings affect the “K” trimming factor by ~1.2%. Minor
adjustments are made to tune the reference voltage level and
temperature tracking rate to compensate for IC processing
variations.
analog common mode voltage for the differential analog
circuits. The Vcm level is available at a package pin for
external decoupling and should be driven by a 0.9 V supply
(refer to Table 44 on page 29). The Vdark or “black” level
reference supplied from an on-chip SPI programmable DAC
is also buffered and distributed on-chip as input to each of
the 64 AFE and ADC channels. This signal is also available
at a package pin for external decoupling. Separate power
down control bits are available for the differential ADC
reference (Vrefp–Vrefm), Vcm, and Vdark. When any of
these are powered down, external references are driven on
the external package pins. Table 14 overviews primary
parameters for the references and biases.
The reference generation circuits also form the internal
At V
At V
ADC range. 3-bit SPI trim settings 1x, 0.95x, 0.91x, 0.83x, 0.77x,
0.71x, 0.67x, 0.5x.
External power supply voltage. Requires 10 nF to gnd.
Refer to Table 44 on page 29.
Must pull down to gnd with ~ 50 kW.
Typical < 50 PPM. Level and tracking are 3-bit SPI trimmable. Five
settings at ~ 1.2% adjust per step.
DD
DD
= 2.5 V. Requires 0.01 mF to gnd.
= 2.5 V. Requires 0.01 mF to gnd.
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