SC28L92A1A,518 NXP Semiconductors, SC28L92A1A,518 Datasheet - Page 31

• Manufacturer Part Number: SC28L92A1A,518
• Description: IC UART DUAL W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L92A1A,518

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935263293518; SC28L92A1A-T; SC28L92A1A-T

NXP Semiconductors
SC28L92_7
Product data sheet
Table 31.
Table 32.
Mode
Normal
Automatic
echo
Local
loopback
Remote
loopback
MR2A[3:0] (hexadecimal)
0
1
2
3
4
5
6
7
8
9
A
DUART mode description
Stop bit length
Description
The transmitter and receiver operating independently.
Places the channel in the automatic echo mode, which automatically retransmits the
received data. The following conditions are true while in automatic echo mode:
Selects local loopback diagnostic mode. In this mode:
Selects remote loopback diagnostic mode. In this mode:
1. Received data is reclocked and retransmitted on the TxDA output
2. The receive clock is used for the transmitter
3. The receiver must be enabled, but the transmitter need not be enabled
4. The channel A TxRDY and TxEMT status bits are inactive
5. The received parity is checked, but is not regenerated for transmission, i.e.
6. Character framing is checked, but the stop bits are retransmitted as received
7. A received break is echoed as received until the next valid start bit is detected
8. CPU to receiver communication continues normally, but the CPU to transmitter
1. The transmitter output is internally connected to the receiver input
2. The transmit clock is used for the receiver
3. The TxDA output is held HIGH
4. The RxDA input is ignored
5. The transmitter must be enabled, but the receiver need not be enabled
6. CPU to transmitter and receiver communications continue normally
1. Received data is reclocked and retransmitted on the TxDA output
2. The receive clock is used for the transmitter
3. Received data is not sent to the local CPU, and the error status conditions are
4. The received parity is not checked and is not regenerated for transmission, i.e.,
5. The receiver must be enabled
6. Character framing is not checked, and the stop bits are retransmitted as received
7. A received break is echoed as received until the next valid start bit is detected
transmitted parity bit is as received
link is disabled
inactive
transmitted parity is as received
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Stop bit length
0.563
0.625
0.688
0.750
0.813
0.875
0.938
1.000
1.563
1.653
1.688
[1]
SC28L92
© NXP B.V. 2007. All rights reserved.
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