SC28L198A1BE,557 NXP Semiconductors, SC28L198A1BE,557 Datasheet - Page 20

• Manufacturer Part Number: SC28L198A1BE,557
• Description: IC UART OCTAL W/FIFO 100-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC28L198A1BE,557

• Features: False-start Bit Detection
• Number Of Channels: 8
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1210; 935262731557; SC28L198A1BE

Philips Semiconductors
the status for all characters coming to the top of the FIFO, since the
last reset error command was issued.
MR1[4:3]: Parity Mode Select
If ’with parity’ or ’force parity’ is selected, a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data. MR1[4:3] = 11 selects the channel to operate in the
special wake up mode.
MR1[2]: Parity Type Select
This bit sets the parity type (odd or even) if the ’with parity’ mode is
Table 5. MR2 – Mode Register 2
The MR2 register provides basic channel setup control that may need more frequent updating.
MR2[7:6] – Mode Select
The Octal UART can operate in one of four modes: MR2[7:6] = b’00
is the normal mode, with the transmitter and receiver operating
independently.
MR2[7:6] = b’01 places the channel in the automatic echo mode,
which automatically re transmits the received data. The following
conditions are true while in automatic echo mode:
. CPU to receiver communication continues normally, but the CPU
to transmitter link is disabled.
Two diagnostic modes can also be selected.
MR2[7:6] = b’10 selects local loop back mode. In this mode:
The second diagnostic mode is the remote loop back mode,
selected by MR2[7:6] = b’11. In this mode:
2006 Aug 10
Bits 7:6
Channel Mode
00 = normal
01 = Auto echo
10 = Local loop
11 = Remote loop
Octal UART for 3.3 V and 5 V supply voltage
Received data is re–clocked and re–transmitted on the TxD
output.
The receive clock is used for the transmitter.
The receiver must be enabled, but the transmitter need not be
enabled.
The TxRDY and TxEMT status bits are inactive.
The received parity is checked, but is not regenerated for
transmission,
i.e., transmitted parity bit is as received.
Character framing is checked, but the stop bits are re-transmitted
as received.
A received break is echoed as received until the next valid start
bit is detected
The transmitter output is internally connected to the receiver
input.
The transmit clock is used for the receiver.
The TxD output is held high.
The RxD input is ignored.
The transmitter must be enabled, but the receiver need not be
enabled.
CPU to transmitter and receiver communications continue
normally.
Received data is re–clocked and re–transmitted on the TxD
output.
The receive clock is used for the transmitter.
Received data is not sent to the local CPU, and the error status
conditions are inactive.
Bit 5
TxRTS Control
0 = No
1 = Yes
Bit 4
CTSN Enable Tx
0 = No
1 = Yes
20
programmed by MR1[4:3], and the polarity of the forced parity bit if
the ’force parity’ mode is programmed. It has no effect if the ’no
parity’ mode is programmed. In the special ’wake up’ mode, it
selects the polarity of the A/D bit. The parity bit is used to an
address or data byte in the ’wake up’ mode.
MR1[1:0]: Bits per Character Select
This field selects the number of data bits per character to be
transmitted and received. This number does not include the start,
parity, or stop bits.
MR2[5] – Transmitter Request to Send Control
This bit controls the deactivation of the RTSN output (I/O2) by the
transmitter. This output is manually asserted and negated by
appropriate commands issued via the command register. MR2[5] =
1 causes RTSN to be reset automatically one bit time after the
characters in the transmit shift register and in the TxFIFO (if any)
are completely transmitted (includes the programmed number of
stop bits if the transmitter is not enabled). This feature can be used
to automatically terminate the transmission of a message as follows:
NOTE: When the transmitter controls the RTSN pin, the meaning of
the pin is COMPLETELY changed. It has nothing to do with the
normal RTSN/CTSN “handshaking”. It is usually used to mean “end
of message” and to “turn the line around” in simplex
communications.
MR2[4] – Clear to Send Control
The state of this bit determines if the CTSN input (I/O0) controls the
operation of the transmitter. If this bit is 0, CTSN has no effect on
The received parity is not checked and is not regenerated for
transmission, i.e., the transmitted parity bit is as received.
The receiver must be enabled, but the transmitter need not be
enabled.
Character framing is not checked, and the stop bits are
re-transmitted as received.
A received break is echoed as received until the next valid start
bit is detected.
Program auto reset mode: MR2[5]= 1.
Enable transmitter.
Assert RTSN via command.
Send message.
After the last character of the message is loaded to the TxFIFO,
disable the transmitter. Before disabling the transmitter be sure
the Status Register TxEMT bit is NOT set (i.e., the transmitter is
not underrun). The underrun condition is indicated by the
TxEMT bit in the SR being set. The condition occurs
immediately upon enabling the transmitter and persists until a
character is loaded to the TxFIFO. The Underrun condition will
not be a problem as long as the controlling processor keeps up
with the transmitter data flow. The proper operation of this
feature assumes that the transmitter is busy (not underrun) when
the disable is issued.
The last character will be transmitted and RTSN will be reset one
bit time after the last stop bit.
Bit 3:2
RxINT
00 = RRDY
01 = Half Full
10 = 3/4 Full
11 = Full
Bit 1:0
Stop Length
00 = 1.0
01 = 1.5
10 = 2.0
11 = 9/16
SC28L198
Product data sheet