SC28L198A1BE,557 NXP Semiconductors, SC28L198A1BE,557 Datasheet - Page 31

• Manufacturer Part Number: SC28L198A1BE,557
• Description: IC UART OCTAL W/FIFO 100-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC28L198A1BE,557

• Features: False-start Bit Detection
• Number Of Channels: 8
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1210; 935262731557; SC28L198A1BE

Philips Semiconductors
The registers of the SC28L198 are partitioned into two groups: those
used in controlling data channels and those used in handling the
actual data flow and status. Below is shown the general
configuration of all the register addressed. The ”Register Map
Summary” shows the configuration of the lower four bits of the
address that is the same for the individual UARTs. It also shows the
addresses for the several in the address space of UART A and
REGISTER MAP SUMMARY
Table 43. Summary Register Map, Control
2006 Aug 10
REGISTER MAPS
0ccc 0000 (x00)
0ccc 0001 (x01)
0ccc 0010 (x02)
0ccc 0011 (x03)
0ccc 0100 (x04)
0ccc 0110 (x06)
0ccc 0111 (x07)
0ccc 1000 (x08)
0ccc 1001 (x09)
0ccc 1010 (x0A)
0ccc 1100 (x0C)
0000 1101 (x0D)
0ccc 1110 (x0E)
0000 1111 (x0F)
0001 1011 (x1B)
0001 1101 (x1D)
0001 1111 (x1F)
Octal UART for 3.3 V and 5 V supply voltage
Address (hex) ccc = channel
GPORQN
4:1 MULTIPLEX
4:1 MULTIPLEX
1/O3a
1/O3b
NONE
G
G
GPOD
IN
IN
“1”
“0”
GPOC
0
1
4
DATA BUS 3:0
GPOR R/W
4
Mode Register 0 MR0a
Mode Register 1 MR1a
I/O Port Configuration Reg a I/OPCRa
Bid Control, Break Change
Bid Control, Change of State
Bid Control, Xon/Xoff
Bid Control, Address recognition
Xon Character Register
Xoff Character Register
Address Recognition Character
Receiver Clock Select Register
Transmitter Clock Select Register
Figure 1. General Purpose Pin Control Logic
DATA IN/OUT
DATA READ/WRITE
D INPUT
Test Register
Global Chip Configuration Register
Interrupt Control Register
Watch-dog Timer Run Control
Interrupt Vector Register
D CLOCK
GPOR
QN
Register Name
31
RxC16Xa
TxC16Xa
TxC16Xb
4
TxC1Xa
UART B that apply to the total chip configuration. The ”Register
Map Detail” shows the use of every address in the 8 bit address
space.
NOTE: The register maps for channels A and B (UARTs A and B)
contain some control registers that configure the entire chip. These
are denoted by a
GPOR(0)
GPOR(1)
GPOR(2)
GPOR(3)
8:1 MULTIPLEX
GPOSR
symbol.
Reserved, set to 0
WDTRCR
Acronym
BCRCOS
BCRBRK
RxCSR
IOPCR
XonCR
XoffCR
TxCSR
GCCR
BCRX
BCRA
ARCR
MR0
MR1
ICR
IVR
SC28L198
GPO PIN
Product data sheet
SD00526
Read / Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W