SC28L198A1A,512 NXP Semiconductors, SC28L198A1A,512 Datasheet - Page 41
![IC UART OCTAL W/FIFO 84-PLCC](/photos/6/98/69866/568-84-plcc_sot189-2_sml.jpg)
SC28L198A1A,512
Manufacturer Part Number
SC28L198A1A,512
Description
IC UART OCTAL W/FIFO 84-PLCC
Manufacturer
NXP Semiconductors
Datasheet
1.SC28L198A1BE557.pdf
(57 pages)
Specifications of SC28L198A1A,512
Features
False-start Bit Detection
Number Of Channels
8
Fifo's
16 Byte
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
84-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1117-5
935261323512
SC28L198A1A
935261323512
SC28L198A1A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC28L198A1A,512
Manufacturer:
TI
Quantity:
159
Company:
Part Number:
SC28L198A1A,512
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
RESET CONDITIONS
Device Configuration after Hardware Reset or CRa
cmd=x1F
Cleared registers:
Clears Modes for:
2006 Aug 10
Octal UART for 3.3 V and 5 V supply voltage
Channel Status Registers (SR)
Channel Interrupt Status Registers (ISR)
Channel Interrupt Mask Registers (IMR)
Channel Interrupt Xon Status Register (XISR)
Interrupt Control Register (ICR)
Global Configuration Control Register (GCCR)
Hence the device enters the asynchronous bus cycling mode.
Current Interrupt Register (CIR)
BRG Timer Run Control Register (BRGTCR)
Watch-dog Timer Run Control Register (WDTRCR)
Channel Input/Output Port Configuration Registers (I/OPCR)
Hence all I/O pins have direction = Input after reset
BRG Counter/Timer Registers
Power down
41
Disables:
Halts:
Limitations:
Test modes
Input Port Changed bits
Gang write to Xon or Xoff
Xon/Xoff/Address detection
Receiver error status
Transmitters
Receivers
Interrupts, current and future
BRG Counters
Bus cycle in progress (hardware RESET only)
Minimum RESETN pin pulse width is 10 SClk cycles after Vcc
reaches operational range
The user must allow a minimum of 6 SClk cycles to elapse after
a reset (RESETN pin or CRa initiated) of the device terminates
before initiating a new bus cycle.
SC28L198
Product data sheet