SC28L198A1A,512 NXP Semiconductors, SC28L198A1A,512 Datasheet - Page 9
![IC UART OCTAL W/FIFO 84-PLCC](/photos/6/98/69866/568-84-plcc_sot189-2_sml.jpg)
SC28L198A1A,512
Manufacturer Part Number
SC28L198A1A,512
Description
IC UART OCTAL W/FIFO 84-PLCC
Manufacturer
NXP Semiconductors
Datasheet
1.SC28L198A1BE557.pdf
(57 pages)
Specifications of SC28L198A1A,512
Features
False-start Bit Detection
Number Of Channels
8
Fifo's
16 Byte
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
84-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1117-5
935261323512
SC28L198A1A
935261323512
SC28L198A1A
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Quantity
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Philips Semiconductors
value”. They may, however, be loaded by a “Gang White” or “Gang
Load” command as described in the “Xon Xoff Characters”
paragraph.
Note: Character recognition is further described in the Minor Modes
of Operation.
Interrupt Control
The interrupt system determines when an interrupt should be
asserted thorough an arbitration (or bidding) system. This
arbitration is exercised over the several systems within the OCTART
that may generate an interrupt. These will be referred to as
”interrupt sources”. There are 64 in all. In general the arbitration is
based on the fill level of the receiver FIFO or the empty level of the
transmitter FIFO. The FIFO levels are encoded into a four bit
number which is concatenated to the channel number and source
identification code. All of this is compared (via the bidding or
arbitration process) to a user defined ”threshold”. When ever a
source exceeds the numerical value of the threshold the interrupt
will be generated.
At the time of interrupt acknowledge (IACKN) the source which has
the highest bid (not necessarily the source that caused the interrupt
to be generated) will be captured in a ”Current Interrupt Register”
(CIR). This register will contain the complete definition of the
interrupting source: channel, type of interrupt (receiver, transmitter,
change of state, etc.), and FIFO fill level. The value of the bits in the
CIR are used to drive the interrupt vector and global registers such
that controlling processor may be steered directly to the proper
service routine. A single read operation to the CIR provides all the
information needed to qualify and quantify the most common
interrupt sources.
The interrupt sources for each channel are listed below.
Associated with the interrupt system are the interrupt mask register
(IMR) and the interrupt status register (ISR) resident in each UART.
Programming of the IMR selects which of the above sources may
enter the arbitration process. Only the bidders in the ISR whose
associated bit in the IMR is set to one (1) will be permitted to enter
the arbitration process. The ISR can be read by the host CPU to
determine all currently active interrupting conditions. For
convenience the bits of the ISR may be masked by the bits of the
IMR. Whether the ISR is read unmasked or masked is controlled by
the setting of bit 6 in MR1.
Global Registers
The “Global Registers”, 19 in all, are driven by the interrupt system.
These are not real hardware devices. They are defined by the
content of the CIR (Current Interrupt Register) as a result of an
interrupt arbitration. In other words they are indirect registers
contained in the Current Interrupt Register (CIR) which the CIR uses
to point to the source and context of the OCTART sub circuit
2006 Aug 10
Transmit FIFO empty level for each channel
Receive FIFO Fill level for each channel
Change in break received status for each channel
Receiver with error for each channel
Change of state on channel input pins
Receiver Watch-dog Time–out Event
Xon/Xoff character recognition
Address character recognition
Octal UART for 3.3 V and 5 V supply voltage
9
presently causing an interrupt. The principle purpose of these
”registers” is improving the efficiency of the interrupt service.
The global registers and the CIR update procedure are further
described in the Interrupt Arbitration system
I/O Ports
Each of the eight UART blocks contains an I/O section of four ports.
These ports function as a general purpose post section which
services the particular UART they are associated with. External
clocks are input and internal clocks are output through these ports.
Each of the four pins has a change of state detector which will signal
a change (0 to 1 or 1 to 0) at the pin. The change of state detectors
are individually enabled and may be set to cause and interrupt.
These pins will normally be used for flow control hand–shaking and
the interface to a modem. Their control is further described in I/O
Ports section and the I/OPCR register.
DETAILED DESCRIPTIONS
RECEIVER AND TRANSMITTER
The Octal UART has eight full-duplex asynchronous
receiver/transmitters. The operating frequency for the receiver and
transmitter can be selected independently from the baud rate
generator, the counter , or from an external input. Registers that are
central to basic full-duplex operation are the mode registers (MR0,
MR1 and MR2), the clock select registers (RxCSR and TxCSR), the
command register (CR), the status register (SR), the transmit
holding register (TxFIFO), and the receive holding register
(RxFIFO).
Transmitter
The transmitter accepts parallel data from the CPU and converts it
to a serial bit stream on the TxD output pin. It automatically sends a
start bit followed by the programmed number of data bits, an
optional parity bit, and the programmed number of stop bits. The
least significant bit is sent first. Each character is always ”framed”
by a single start bit and a stop bit that is 9/16 bit time or longer. If a
new character is not available in the TxFIFO, the TxD output
remains high, the ”marking” position, and the TxEMT bit in the SR is
set to 1.
Transmitter Status Bits
The SR (Status Register, one per UART) contains two bits that show
the condition of the transmitter FIFO. These bits are TxRDY and
TxEMT. TxRDY means the TxFIFO has space available for one or
more bytes; TxEMT means The TxFIFO is completely empty and
the last stop bit has been completed. TxEMT can not be active
without TxRDY also being active. These two bits will go active upon
initial enabling of the transmitter. They will extinguish on the disable
or reset of the transmitter.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads at least one new character into the TxFIFO. The TxRDY will
not extinguish until the TxFIFO is completely full. The TxRDY bit will
always be active when the transmitter is enabled and there is at
lease one open position in the TxFIFO.
The transmitter is disabled by reset or by a bit in the command
register (CR). The transmitter must be explicitly enabled via the CR
before transmission can begin. Note that characters cannot be
loaded into the TxFIFO while the transmitter is disabled, hence it is
necessary to enable the transmitter and then load the TxFIFO. It is
not possible to load the TxFIFO and then enable the transmission.
Note the difference between transmitter disable and transmitter
reset. The transmitter may by reset by a hardware or software. The
SC28L198
Product data sheet