MAX3107ETG+ Maxim Integrated Products, MAX3107ETG+ Datasheet - Page 23

• Manufacturer Part Number: MAX3107ETG+
• Description: IC UART SPI/I2C 128 FIFO 24TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX3107ETG+

• Features: Internal Oscillators
• Number Of Channels: 4, QUART
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.35 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Data Rate: 24 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 2.35 V
• Supply Current: 0.64 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 1
• Uart Features: 128-Word Transmit / Receive FIFO, Half-Duplex Echo Suppression, Shutdown And Autosleep Modes
• Supply Voltage Range: 2.35V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RHR—Receiver Hold Register
The structure of the interrupt is shown in Figure 13. There
are four interrupt source registers: ISR, LSR, STSInt, and
SpclCharInt. The interrupt sources are divided into top-
level and low-level interrupts. The top-level interrupts
typically occur more often and can be read out directly
through the ISR. The low-level interrupts typically occur
less often and their specific source can be read out
through the LSR, STSInt, or SpclChar registers. The three
LSBs of the ISR point to the low-level interrupt registers
that contain the source detail of the interrupt source.
Every interrupt bit of the four interrupt registers can be
enabled or masked through an associated interrupt
Bits 7–0: RData[7:0]
The RHR is the bottom of the receive FIFO and is the register used for reading data out of the receive FIFO. It contains
the oldest (first received) character in the receive FIFO. RHR[0] is the LSB of the character received at the RX input. It
is the first data bit of the serial-data word received by the receiver.
Figure 13. Simplified Interrupt Structure
ADDRESS:
MODE:
RESET
NAME
BIT
7
6
RData7
______________________________________________________________________________________
7
0
5
4
STSInt
8
3
0x00
R
RData6
2
SPI/I
Interrupt Structure
6
0
LOW-LEVEL INTERRUPTS
1
7
Interrupt Enabling
0
6
RData5
2
5
5
0
7
C UART with 128-Word FIFOs
4
8
ISR
6
3
5
[7]
[0]
2
RData4
SpclChrInt
4
8
4
0
1
3
enable register bit. These are the IRQEn, LSRIntEn,
SpclChrIntEn and STSIntEn registers.
When an ISR interrupt is pending (i.e., any bit in ISR is
set) and the ISR is subsequently read, the ISR bits and
IRQ are cleared. Both the SpclCharInt and the STSInt
registers also are clear on read (COR). The LSR bits are
only cleared when the source of the interrupt is removed,
not when LSR is read.
The MAX3107 has a flat register structure, without shad-
ow registers, that makes programming and code simple
and efficient. All registers are 8 bits wide.
and Internal Oscillator
0
2
TOP-LEVEL INTERRUPTS
1
RData3
3
0
0
IRQ
Detailed Register Descriptions
7
RData2
6
2
0
5
4
8
LSR
3
RData1
1
0
2
Interrupt Clearing
1
0
RData0
0
0
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