SC16C850SVIBS,115 NXP Semiconductors, SC16C850SVIBS,115 Datasheet - Page 31

• Manufacturer Part Number: SC16C850SVIBS,115
• Description: IC UART SGL 1.8V W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850SVIBS,115

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286785115; SC16C850SVIBS-G; SC16C850SVIBS-G

NXP Semiconductors
SC16C850SV
Product data sheet
7.17 Flow Control Trigger Level High (FLWCNTH)
7.18 Flow Control Trigger Level Low (FLWCNTL)
7.19 Clock prescaler (CLKPRES)
[1]
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control.
register bit settings; see
Table 27.
[1]
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control.
register bit settings; see
Table 28.
[1]
This register hold values for the clock prescaler.
Table 29.
Bit
7:0
Bit
7:0
Bit
7:4
3:0
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
FLWCNTH[7:0]
Symbol
Symbol
FLWCNTL[7:0]
Symbol
CLKPRES[7:4]
CLKPRES[3:0]
FLWCNTH register bits description
FLWCNTL register bits description
Clock prescaler register description
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 22 March 2011
Section
Section
Description
This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO mode.
Description
This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO mode.
Description
reserved
clock prescaler value; reset to 0
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Section 7.3 “FIFO Control Register
Section 7.3 “FIFO Control Register
Section 7.3 “FIFO Control Register
6.5.
6.5.
Table 27
Table 28
(FCR)”.
(FCR)”.
(FCR)”.
SC16C850SV
shows transmission control
shows transmission control
© NXP B.V. 2011. All rights reserved.
[1]
[1]
31 of 48