NS16C2552TVAX/NOPB National Semiconductor, NS16C2552TVAX/NOPB Datasheet - Page 20

• Manufacturer Part Number: NS16C2552TVAX/NOPB
• Description: IC UART DUAL 16BYTE 44-PLCC
• Manufacturer: National Semiconductor

Specifications of NS16C2552TVAX/NOPB

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NS16C2552TVAX

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6.8 LINE STATUS REGISTER (LSR)
This register provides status information to the CPU concern-
ing the data transfer.
Bit
7
6
5
4
3
Rx Frame Error
Rx FIFO Err
THR & TSR
THR Empty
Bit Name
Rx Break
Interrupt
Empty
R/W
Def
R
R
R
R
R
0
1
1
0
0
Rx FIFO Data Error
This bit is a global Rx FIFO error flag. In the 16450 Mode this bit is 0.
1 = A sum of all error bits in the Rx FIFO. These errors include parity, framing, and break indication
in the FIFO data.
0 = No Rx FIFO error (default).
Note: The Line Status Register is intended for read operations only. Writing to this register is not recommended as this
THR and TSR Empty
This bit is the Transmitter Empty (TEMT) flag.
1 = Whenever the Transmitter Holding Register (THR) (or the Tx FIFO in FIFO mode) and the
Transmitter Shift Register (TSR) are both empty (default).
0 = Whenever either the THR (or the Tx FIFO in FIFO mode) or the TSR contains a data word.
THR Empty
This bit is the Transmitter Holding Register Empty (THRE) flag. In the 16450 mode bit 5 indicates
that the associated serial channel is ready to accept a new character for transmission. In addition,
this bit causes the DUART to issue an interrupt to the CPU when the Transmit Holding Register
Empty interrupt enable is set.
1 = In 16450 mode, whenever a character is transferred from the Transmitter Holding Register
into the Transmitter Shift Register, or in FIFO mode when the Tx FIFO is empty (default).
0 = In 16450 mode, this bit is reset to logic 0 concurrently with the loading of the Transmitter
Holding Register by the CPU. In FIFO mode, it is cleared when at least 1 byte is written to the Tx
FIFO.
Receive Break Interrupt Indicator
This bit is the Break Interrupt (BI) indicator.
1 = Whenever the received data input is held in the Spacing (logic 0) state for longer than a full
frame transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).
0 = No break condition (default).
This bit is reset to 0 whenever the CPU reads the contents of the Line Status Register or when
the next valid character is loaded into the Receiver Buffer Register.
In the FIFO Mode this condition is associated with the particular character in the FIFO it applies
to. It is revealed to the CPU when its associated character is at the top of the FIFO. When break
occurs only one zero character is loaded into the FIFO. The next character transfer is enabled
after SIN goes to the Marking (logic 1) state and receives the next valid start bit.
Framing Error Indicator
This bit is the Framing Error (FE) indicator.
1= Received character did not have a valid Stop bit when the serial channel detects a logic 0 during
the first Stop bit time.
0 = No frame error (default).
The bit is reset to 0 whenever the CPU reads the contents of the Line Status Register or when the
next valid character is loaded into the Receiver Buffer Register. In the FIFO Mode this error is
associated with the particular character in the FIFO it applies to. This error is revealed to the CPU
when its associated character is at the top of the FIFO. The serial channel will try to resynchronize
after a framing error. This assumes that the framing error was due to the next start bit, so it samples
this start bit twice and then takes in the data.
operation is only used for factory testing.
TABLE 12. LSR (0x5)
20
Bits 1 through 4 are the error conditions that produce a Re-
ceiver Line Status interrupt whenever any of the correspond-
ing conditions are detected and the interrupt is enabled.
Description