NS16C2752TVS/NOPB National Semiconductor, NS16C2752TVS/NOPB Datasheet - Page 11

• Manufacturer Part Number: NS16C2752TVS/NOPB
• Description: IC UART DUAL 64BYTE 48-TQFP
• Manufacturer: National Semiconductor

Specifications of NS16C2752TVS/NOPB

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NS16C2752TVS

Default
Default
Default
Default
Default
Default
XOFF1
Default
XOFF2
Default
A2-A0
DREV
XON1
XON2
Addr
DLM
AFR
EFR
Reg
DLL
0x0
0x1
0x2
0x0
0x2
0x4
0x5
0x6
0x7
The Nomenclature of register descriptions:
•
•
•
•
Register name, address, register bit, and value example:
FCR 0x2.7:6 = 2’b11 - bits 6 and 7 of FCR are both 1.
Alternative description: FCR[7:6] = 2’b11.
‘b - binary number.
‘h - hex number.
0xNN - hex number.
Bit
7:0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RD/
WR
R
Legend
XOFF1 XOFF1 XOFF1
XOFF2 XOFF2 XOFF2
XON1
XON2
Rsrvd
BIT 7
DLM
Auto
Bit 7
Bit 7
Bit 7
Bit 7
CTS
Bit 7
Bit 7
Bit 7
Bit 7
DLL
Ena
ID
X
X
0
0
0
0
0
0
RBR Data
Bit Name
Default
XON1
XON2
Rsrvd
Name
Value
BIT 6
Bit 6
DLM
Bit 6
Bit 6
Bit 6
Auto
RTS
Bit 6
Bit 6
Bit 6
Bit 6
DLL
Ena
Bit
ID
X
X
0
0
0
0
0
0
Special
XON1
XON2
Rsrvd
BIT 5
DLM
Char
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
DLL
Sel
ID
X
X
0
0
0
0
0
0
MCR[7:5]
FCR[5:4]
IER[7:4]
IIR[5:4]
XOFF1
XOFF2
R/W Def
XON1
XON2
Rsrvd
BIT 4
Bit 4
DLM
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
DLL
0xXX
Baud Rate Generator Divisor
ID
X
X
0
0
0
0
0
0
R
Enhanced Registers
TABLE 3. RBR (0x0)
Control
XOFF1 XOFF1
XOFF2 XOFF2
DREV
XON1
XON2
Rsrvd
BIT 3
DLM
Flow
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
DLL
SW
X
X
0
0
0
0
0
0
Receive Buffer Register
Rx FIFO data.
Note: This register value does not change upon MR reset.
11
Control
RXRD
DREV
XON1
XON2
BIT 2
DLM
Flow
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
DLL
SW
Sel
•
6.1 RECEIVE BUFFER REGISTER (RBR)
The receiver section contains an 8-bit Receive Shift Register
(RSR) and a 16 (or 64)-byte FIFO that can be accessed
through Receive Buffer Register (RBR).
X
X
Y
0
0
0
0
0
0
n’bN - n is the number of bits; N is the bit value. Example
8’b01010111 = 8’h57 = 0x57.
Control Bit 1
BAUDOUT
SW Flow
XOFF1
XOFF2
DREV
XON1
XON2
BIT 1
DLM
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
DLL
Sel
X
X
0
0
0
0
0
0
Control
XOFF1
XOFF2
Description
current
DREV
XON1
XON2
BIT 0
Con-
DLM
Flow
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
DLL
WR
SW
X
X
0
0
0
0
0
0
LCR != 0xBF
DLM = 0x00
LCR = 0xBF
LCR ! 0xBF
DLL = 0x00
LCR[7] = 1
LCR[7] = 1
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