XC56309PV100A Freescale Semiconductor, XC56309PV100A Datasheet - Page 103

• Manufacturer Part Number: XC56309PV100A
• Manufacturer: Freescale Semiconductor

Specifications of XC56309PV100A

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
;
;
;
;------------------------------------------------------------------------
;
M_PCTL EQU $FFFFFD
;
M_MF EQU $FFF
M_DF EQU $7000
M_XTLR EQU 15
M_XTLD EQU 16
M_PSTP EQU 17
M_PEN EQU 18
M_PCOD EQU 19
M_PD EQU $F00000
;------------------------------------------------------------------------
;
;
;
;------------------------------------------------------------------------
;
M_BCR EQU $FFFFFB
M_DCR EQU $FFFFFA
M_AAR0 EQU $FFFFF9
M_AAR1 EQU $FFFFF8
M_AAR2 EQU $FFFFF7
M_AAR3 EQU $FFFFF6
M_IDR EQU $FFFFF5
;
M_BA0W EQU $1F
M_BA1W EQU $3E0
M_BA2W EQU $1C00
M_BA3W EQU $E000
M_BDFW EQU $1F0000
M_BBS EQU 21
M_BLH EQU 22
M_BRH EQU 23
;
M_BCW EQU $3
M_BRW EQU $C
M_BPS EQU $300
M_BPLE EQU 11
M_BME EQU 12
M_BRE EQU 13
M_BSTR EQU 14
M_BRF EQU $7F8000
EQUATES for Phase Locked Loop (PLL)
Register Addresses Of PLL
PLL Control Register
EQUATES for BIU
Register Addresses Of BIU
Bus Control Register
DRAM Control Register
DSP56309 Technical Data, Rev. 7
; PLL Control Register
; Multiplication Factor Bits Mask (MF0-MF11)
; Division Factor Bits Mask (DF0-DF2)
; XTAL Range select bit
; XTAL Disable Bit
; STOP Processing State Bit
; PLL Enable Bit
; PLL Clock Output Disable Bit
; PreDivider Factor Bits Mask (PD0-PD3)
; Bus Control Register
; DRAM Control Register
; Address Attribute Register 0
; Address Attribute Register 1
; Address Attribute Register 2
; Address Attribute Register 3
; ID Register
; Area 0 Wait Control Mask (BA0W0-BA0W4)
; Area 1 Wait Control Mask (BA1W0-BA14)
; Area 2 Wait Control Mask (BA2W0-BA2W2)
; Area 3 Wait Control Mask (BA3W0-BA3W3)
; Default Area Wait Control Mask (BDFW0-BDFW4)
; Bus State
; Bus Lock Hold
; Bus Request Hold
; In Page Wait States Bits Mask (BCW0-BCW1)
; Out Of Page Wait States Bits Mask (BRW0-BRW1)
; DRAM Page Size Bits Mask (BPS0-BPS1)
; Page Logic Enable
; Mastership Enable
; Refresh Enable
; Software Triggered Refresh
; Refresh Rate Bits Mask (BRF0-BRF7)
A-13