XC56309PV100A Freescale Semiconductor, XC56309PV100A Datasheet - Page 88

• Manufacturer Part Number: XC56309PV100A
• Manufacturer: Freescale Semiconductor

Specifications of XC56309PV100A

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Design Considerations
One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to minimize
specific board effects (that is, to compensate for measured board current not caused by the DSP). A benchmark
power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current
measurements, and the following equation to derive the current-per-MIPS value.
Where:
Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The
4.4 PLL Performance Issues
The following explanations should be considered as general observations on expected PLL behavior. There is no
test that replicates these exact numbers. These observations were measured on a limited number of parts and were
not verified over the entire temperature and voltage ranges.
4.4.1
The phase skew of the PLL is defined as the time difference between the falling edges of
given capacitive load on
2, External Clock Timing, on page 2-5 for input frequencies greater than 15 MHz and the MF ≤4, this skew is
greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10
and input frequencies greater than 10 MHz, this skew is between − 1.4 ns and +3.2 ns.
4.4.2
The phase jitter of the PLL is defined as the variations in the skew between the falling edges of
for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on
variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF ≤ 4, this
jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies
greater than 10 MHz, this jitter is less than ±2 ns.
4.4.3
The frequency jitter of the PLL is defined as the variation of the frequency of
this jitter is smaller than 0.5 percent. For mid-range MF (10 < MF < 500) this jitter is between 0.5 percent and
approximately 2 percent. For large MF (MF > 500), the frequency jitter is 2–3 percent.
4-4
6.
7.
degree of difference between F1 and F2 determines the amount of precision with which the current rating
can be determined for an application.
Equation 5:
Disable unused peripherals.
Disable unused pin activity (for example,
Phase Skew Performance
Phase Jitter Performance
Frequency Jitter Performance
⁄
I
I
F2
F1
CLKOUT
typF2
typF1
MIPS
=
=
=
=
=
, over the entire process, temperature and voltage ranges. As defined in Figure 2-
I
⁄
MHz
current at F2
current at F1
high frequency (any specified operating frequency)
low frequency (any specified operating frequency lower than F2)
DSP56309 Technical Data, Rev. 7
=
(
I
typF2
–
I
typF1
CLKOUT
)
⁄
(
F2 F1
,
XTAL
–
).
CLKOUT
. For small MF (MF < 10)
EXTAL
Freescale Semiconductor
EXTAL
CLKOUT
and
CLKOUT
and
. These
CLKOUT
for a