SC16C2552IA44,529 NXP Semiconductors, SC16C2552IA44,529 Datasheet - Page 21

• Manufacturer Part Number: SC16C2552IA44,529
• Description: IC UART DUAL W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors

Specifications of SC16C2552IA44,529

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1186-5; 935270026529; SC16C2552IA44-S

Philips Semiconductors
9397 750 11636
Product data
7.8 Modem Status Register (MSR)
Table 17:
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C2552 is connected. Four bits
of this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a control input from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
Table 18:
[1]
Bit
0
Bit
7
6
5
4
3
2
1
0
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
LSR[0]
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
MSR[1]
MSR[0]
Line Status Register bits description
Modem Status Register bits description
Description
Receive data ready.
Rev. 03 — 20 June 2003
Description
Carrier Detect, CD. During normal operation, this bit is the complement
of the CD input. Reading this bit in the loop-back mode produces the
state of MCR[3] (OPA/OPB).
Ring Indicator, RI. During normal operation, this bit is the complement of
the RI input. Reading this bit in the loop-back mode produces the state of
MCR[2] (OP1).
Data Set Ready, DSR. During normal operation, this bit is the
complement of the DSR input. During the loop-back mode, this bit is
equivalent to MCR[0] (DTR).
Clear To Send, CTS. During normal operation, this bit is the complement
of the CTS input. During the loop-back mode, this bit is equivalent to
MCR[1] (RTS).
CD
RI
DSR
CTS
Logic 0 = No data in receive holding register or FIFO (normal default
condition).
Logic 1 = Data has been received and is saved in the receive holding
register or FIFO.
Logic 0 = No CD change (normal default condition).
Logic 1 = The CD input to the SC16C2552 has changed state since
the last time it was read. A modem Status Interrupt will be generated.
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C2552 has changed from a logic 0
to a logic 1. A modem Status Interrupt will be generated.
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C2552 has changed state since
the last time it was read. A modem Status Interrupt will be generated.
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the
the last time it was read. A modem Status Interrupt will be generated.
[1]
[1]
[1]
[1]
Dual UART with 16-byte transmit and receive FIFOs
…continued
SC16C2552
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C2552
has changed state since
21 of 38