SC16C554IB64,157 NXP Semiconductors, SC16C554IB64,157 Datasheet - Page 32
![IC UART QUAD W/FIFO 64-LQFP](/photos/6/98/69856/568-64-lqfp_sot314-2_sml.jpg)
SC16C554IB64,157
Manufacturer Part Number
SC16C554IB64,157
Description
IC UART QUAD W/FIFO 64-LQFP
Manufacturer
NXP Semiconductors
Specifications of SC16C554IB64,157
Number Of Channels
4, QUART
Fifo's
16 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
64-LQFP
Transmit Fifo
16Byte
Receive Fifo
16Byte
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Package Type
LQFP
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1321
935270074157
SC16C554IB64
935270074157
SC16C554IB64
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C554IB64,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 13132
Product data
7.8 Modem Status Register (MSR)
Table 19:
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C554/554D is connected.
Four bits of this register are used to indicate the changed information. These bits are
set to a logic 1 whenever a control input from the modem changes state. These bits
are set to a logic 0 whenever the CPU reads this register.
Table 20:
Bit
0
Bit
7
6
5
4
3
2
Symbol
LSR[0]
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
Line Status Register bits description
Modem Status Register bits description
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Description
Receive data ready.
Description
CD (Active-HIGH, logical 1). Normally this bit is the complement of the
CD input. In the loop-back mode this bit is equivalent to the OP2 bit in the
MCR register.
RI (Active-HIGH, logical 1). Normally this bit is the complement of the RI
input. In the loop-back mode this bit is equivalent to the OP1 bit in the
MCR register.
DSR (Active-HIGH, logical 1). Normally this bit is the complement of the
DSR input. In loop-back mode this bit is equivalent to the DTR bit in the
MCR register.
CTS. CTS functions as hardware flow control signal input if it is enabled
via EFR[7]. The transmit holding register flow control is enabled/disabled
by MSR[4]. Flow control (when enabled) allows starting and stopping the
transmissions based on the external modem CTS signal. A logic 1 at the
CTS pin will stop SC16C554/554D transmissions as soon as current
character has finished transmission. Normally MSR[4] is the complement
of the CTS input. However, in the loop-back mode, this bit is equivalent to
the RTS bit in the MCR register.
Rev. 05 — 10 May 2004
CD
RI
Logic 0 = No data in receive holding register or FIFO (normal default
condition).
Logic 1 = Data has been received and is saved in the receive holding
register or FIFO.
Logic 0 = No CD change (normal default condition).
Logic 1 = The CD input to the SC16C554/554D has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C554/554D has changed from a
logic 0 to a logic 1. A modem Status Interrupt will be generated.
[1]
[1]
…continued
SC16C554/554D
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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