SC16C650AIA44,529 NXP Semiconductors, SC16C650AIA44,529 Datasheet - Page 9
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
SC16C650AIA44,529
Manufacturer Part Number
SC16C650AIA44,529
Description
IC UART SINGLE W/FIFO 44-PLCC
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C650AIN40112.pdf
(50 pages)
Specifications of SC16C650AIA44,529
Features
False-start Bit Detection
Number Of Channels
1, UART
Fifo's
32 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3272-5
935270029529
SC16C650AIA44-S
935270029529
SC16C650AIA44-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C650AIA44,529
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
Table 2:
[1]
6. Functional description
9397 750 11622
Product data
Symbol
IOW, IOW
XTAL1
XTAL2
In sleep mode, XTAL2 is left floating.
[1]
Pin description
Pin
PLCC44 LQFP48 DIP40
20, 21
18
19
16, 17
14
15
…continued
The SC16C650A provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data that is required with digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character (character orientated protocol). Data integrity is insured
by attaching a parity bit to the data character. The parity bit is checked by the receiver
for any transmission bit errors. The SC16C650A is fabricated with an advanced
CMOS process to achieve low drain power and high speed requirements.
The SC16C650A is an upward solution that provides 32 bytes of transmit and receive
FIFO memory, instead of none in the 16C450, or 16 in the 16C550. The SC16C650A
is designed to work with high speed modems and shared network environments that
require fast data processing time. Increased performance is realized in the
SC16C650A by the larger transmit and receive FIFOs. This allows the external
processor to handle more networking tasks within a given time. In addition, the four
selectable levels of FIFO trigger interrupt and automatic hardware/software flow
control is uniquely provided for maximum data throughput performance, especially
when operating in a multi-channel environment. The combination of the above greatly
reduces the bandwidth requirement of the external controlling CPU, increases
performance, and reduces power consumption.
The SC16C650A is capable of operation up to 3 Mbits/s with a 48 MHz external clock
input (at 5 V).
The rich feature set of the SC16C650A is available through internal registers.
Automatic hardware/software flow control, selectable transmit and receive FIFO
trigger level, selectable TX and RX baud rates, modem interface controls, and a sleep
mode are some of these features.
18, 19 I
16
17
Type
I
O
Rev. 04 — 20 June 2003
Description
Write inputs. When either IOW or IOW is active (LOW or HIGH,
respectively) and while the UART is selected, the CPU is allowed to
write control words or data into a selected UART register. Only one of
these inputs is required to transfer data during a write operation; the
other input should be tied to its inactive level (i.e., IOW tied LOW or
IOW tied HIGH).
Crystal connection or External clock input.
Crystal connection or the inversion of XTAL1 if XTAL1 is driven.
UART with 32-byte FIFO and IrDA encoder/decoder
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C650A
9 of 50