SC16C2550IB48,128 NXP Semiconductors, SC16C2550IB48,128 Datasheet - Page 21
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SC16C2550IB48,128
Manufacturer Part Number
SC16C2550IB48,128
Description
IC DUART SOT313-2
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C2550IN40112.pdf
(46 pages)
Specifications of SC16C2550IB48,128
Features
2 Channels
Number Of Channels
2, DUART
Fifo's
16 Byte
Voltage - Supply
3.5 V ~ 4.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-LQFP
Transmit Fifo
16Byte
Receive Fifo
16Byte
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Package Type
LQFP
Operating Supply Voltage (max)
5.5V
Mounting
Surface Mount
Pin Count
48
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935270020128
SC16C2550IB48-T
SC16C2550IB48-T
SC16C2550IB48-T
SC16C2550IB48-T
Philips Semiconductors
9397 750 11621
Product data
7.4 Interrupt Status Register (ISR)
Table 9:
Table 10:
The SC16C2550 provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. A lower level interrupt may be seen after
servicing the higher level interrupt and re-reading the interrupt status bits.
“Interrupt source”
levels and the interrupt sources associated with each of these interrupt levels.
Table 11:
Bit
1
0
FCR[7]
0
0
1
1
Priority
level
1
2
2
3
4
5
6
ISR[5]
0
0
0
0
0
0
1
FIFO Control Register bits description
RCVR trigger levels
Interrupt source
Symbol
FCR[1]
FCR[0]
FCR[6]
0
1
0
1
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
shows the data values (bits 0-3) for the four prioritized interrupt
ISR[4]
0
0
0
0
0
1
0
Rev. 03 — 19 June 2003
Description
RCVR FIFO reset.
FIFOs enabled.
Logic 0 = Receive FIFO not reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the
FIFO counter logic (the receive shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must
be a ‘1’ when other FCR bits are written to, or they will not
be programmed.
ISR[3]
0
0
1
0
0
0
0
RX FIFO trigger level
01
04
08
14
ISR[2]
1
1
1
0
0
0
0
ISR[1]
1
0
0
1
0
0
0
…continued
ISR[0]
0
0
0
0
0
0
0
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Source of the interrupt
LSR (Receiver Line Status
Register)
RXRDY (Received Data
Ready)
RXRDY (Receive Data
time-out)
TXRDY (Transmitter
Holding Register Empty)
MSR (Modem Status
Register)
RXRDY (Received Xoff
signal) / Special character
CTS, RTS change of state
SC16C2550
encoder/decoder
Table 11
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