LM49370RL/NOPB National Semiconductor, LM49370RL/NOPB Datasheet - Page 29

• Manufacturer Part Number: LM49370RL/NOPB
• Description: IC AUDIO SUBSYSTEM 1.2W 49USMDXT
• Manufacturer: National Semiconductor
• Series: Boomer®, PowerWise®r
• Type: Class Dr

Specifications of LM49370RL/NOPB

• Output Type: 1-Channel (Mono) with Mono and Stereo Headphones
• Max Output Power X Channels @ Load: 1.2W x 1 @ 8 Ohm; 52mW x 2 @ 16 Ohm
• Voltage - Supply: 2.5 V ~ 5.5 V
• Features: 3D, Depop, I²C, I²S, Microphone, Mute, PCM, Shutdown, SPI, Standby, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 49-MicroSMDxt
• Dc: 07+
• For Use With: LM49370RLEVAL - BOARD EVALUATION LM49370RL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM49370RLTR

These tables cover the most common applications, obtaining clocks for derivative sample rates such as 22.05 kHz should be done
by increasing the P divider value or using the R/Q dividers.
An example of obtaining 12.000 MHz from 1.536 MHz is shown below (this is typical for deriving DAC clocks from I2S
datastreams).
Choose a small range of P so that the VCO frequency is swept between 40 MHz and 60 MHz (or 60–80 MHz if VCOFAST is used).
Remembering that the P divider can divide by half integers, for a 12 MHz output, this gives possible P values of 3, 3.5, 4, 4.5, or
5. The M divider should be set such that the comparison frequency (Fcomp) is between 0.5 and 5 MHz. This gives possible M
values of 1, 1.5, 2, 2.5, or 3. The most accurate N and N_MOD can be calculated by sweeping the P and M inputs of the following
formulas:
N = FLOOR(((Fout/Fin)*(P*M)),1)
N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0)
This shows that setting M = 1, N = 39+1/16, P = 5 (i.e. PLL_M = 0, PLL_N = 39, PLL_N_MOD = 2, & PLL_P = 4) gives a comparison
frequency of 1.536MHz, a VCO frequency of 60 MHz and an output frequency of 12.000 MHz. The same settings can be used to
get 11.025 from 1.4112 MHz for 44.1 kHz sample rates.
Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used but an exact
frequency match cannot be found. The I2S should be master on the LM49370 so that the data source can support appropriate
SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems.
Where a system clock exists at an integer multiple of the required ADC or DAC clock rate it is preferable to use this rather than
the PLL. The LM49370 is designed to work in 8, 12, 16, 24, 48 kHz modes from a 12 MHz clock and 8 kHz modes from a 13 MHz
clock without the use of the PLL. This saves power and reduces clock jitter which can affect SNR.
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