AD9500BQ Analog Devices, AD9500BQ Datasheet

AD9500BQ

Manufacturer Part Number

AD9500BQ

Description

7V; 30mA; digitaly programmable delay generator. For ATE, pulse deskewing, arbitary waveform generators

Manufacturer

Analog Devices

Datasheet

1.AD9500BQ.pdf (11 pages)

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GENERAL DESCRIPTION

The AD9500 is a digitally programmable delay generator, which

provides programmed delays, selected through an 8-bit digital

code, in resolutions as small as 10 ps. The AD9500 is con-

structed in a high performance bipolar process, designed to

provide high speed operation for both digital and analog circuits.

The AD9500 employs differential TRIGGER and RESET

inputs which are designed primarily for ECL signal levels but

function with analog and TTL input levels. An onboard ECL

reference midpoint allows both of the inputs to be driven by

either single ended or differential ECL circuits. The AD9500

output is a complementary ECL stage, which also provides a

parallel output circuit to facilitate reset timing implementations.

The digital control data is passed to the AD9500 through a

transparent latch controlled by the LATCH ENABLE signal. In

the transparent mode, the internal DAC of the AD9500 will

attempt to follow changes at the inputs. The LATCH ENABLE

is otherwise used to strobe the digital data into the AD9500

latches.

The AD9500 is available as an industrial temperature range

device, –25 C to +85 C, and as an extended temperature range

device, –55 C to +125 C. Both grades are packaged in a 24-lead

cerdip (0.3" package width), as well as 28-leaded and leadless

surface mount packages. The AD9500 is available in versions

compliant with MIL-STD-883. Refer to the Analog Devices

Military Products Databook or current AD9500/883B data

sheet for detailed specifications.

REV. D

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

FEATURES

10 ps Delay Resolution

2.5 ns to 10 s Full-Scale Range

Fully Differential Inputs

Separate Trigger and Reset Inputs

Low Power Dissipation—310 mW

MIL-STD-883 Compliant Versions Available

APPLICATIONS

ATE

Pulse Deskewing

Arbitrary Waveform Generators

High Stability Timing Source

Multiple Phase Clock Generators

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

TRIGGER

ECL

RESET

SET

OFFSET ADJUST

REF

–V

OFFSET ADJUST

TRIGGER

–V

ECL

DIFFERENTIAL

(MSB)

REFERENCE

CURRENT

FUNCTIONAL BLOCK DIAGRAM

VOLTAGE

ANALOG

TRIGGER

REF

STAGE

INPUT

ECL

RESET

(MSB)

Digitally Programmable

GROUND

REF

PIN CONFIGURATIONS

World Wide Web Site: http://www.analog.com

(LSB)

(Not to Scale)

AD9500

(Not to Scale)

TOP VIEW

AD9500

14 15

TOP VIEW

Delay Generator

CONTROL

INTERNAL DAC

TTL LATCHES

CIRCUIT

TIMING

28 27 26

EXT

17 18

NC = NO CONNECT

AD9500

LATCH ENABLE

–V

ECL COMMON

GROUND

AD9500

(MSB)

(LSB)

LATCH ENABLE

GROUND

–V

ECL COMMON

ENABLE

ECL COMMON

LATCH

(LSB)

OFFSET

ADJUST

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AD9500BQ Summary of contents

Page 1

... Military Products Databook or current AD9500/883B data sheet for detailed specifications. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...

Page 2

AD9500–SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Positive Supply Voltage (+ Negative Supply Voltage (– ...

Page 3

... I + +25 C 150 = Temperature Model Ranges AD9500BP – +85 C AD9500BQ – +85 C AD9500TE – +125 C 28-Leaded LCC, AD9500TQ – +125 C 24-Lead Cerdip, –3– AD9500 – +125 C AD9500TE/TQ Max Min Typ Max Units –1.2 –1.4 –1.3 –1.2 V 1.1 mV/ C –2 mA – ...

Page 4

AD9500 Pin Name Description D –D One of eight digital inputs used to set the programmed delay (MSB) One of eight digital inputs used to set the programmed delay digital input word. ECL ECL midpoint ...

Page 5

DIE LAYOUT REV. D Figure 1. System Timing Diagram MECHANICAL INFORMATION Die Dimensions . . . . . . . . . . . . . . . 104 Pad Dimensions . . . . . . . . . ...

Page 6

AD9500 Figure 2. Input/Output Circuits –6– REV. D ...

Page 7

INSIDE THE AD9500 The heart of the AD9500 is the linear ramp generator. A trig- gering event at the input of the AD9500 initiates the ramp cycle. As the ramp voltage falls, it will eventually go below the thresh- old ...

Page 8

AD9500 APPLICATIONS The AD9500 is a very versatile device that is not difficult to use. Essentially there are only a few basic configurations which can be extended into a number of applications. The TRIGGER and RESET inputs of the AD9500 ...

Page 9

MEASURING UNKNOWN DELAYS Two AD9500s can be combined to measure delays with a high degree of precision. One AD9500 is set with little or no pro- grammed delay, and its output is used to drive the unknown delay circuit, which ...

Page 10

AD9500 LAYOUT CONSIDERATIONS The AD9500 is a precision timing device, and as such high frequency design techniques must be employed to achieve the best performance. The use of a low impedance ground plane is particularly important. Ideally the ground plane ...

Page 11

MAX 0.200 (5.08) 0.125 (3.18) 0.458 (11.63) 0.442 (11.23) 0.048 (1.21) 0.042 (1.07) REV. D OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Cerdip (Q-24) 0.005 (0.13) MIN 0.098 (2.49) MAX 24 13 0.310 (7.87) 0.220 (5.59) ...

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