UPD17225GT NEC, UPD17225GT Datasheet
UPD17225GT
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UPD17225GT Summary of contents
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... Unless otherwise specified, the PD17225 is treated as the representative model throughout this document. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12643EJ2V0DS00 (2nd edition) ...
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... OTP is evaluated on PD17225 subseries board and when WDOUT pin is not used. When PD17P218 is used, malfunctioning does not occur even when WDOUT pin is pulled up, though connection can be changed by using a jumper switch on the external board. Others Supply voltage, low-voltage detection voltage, oscillator characteristics, and noise characteris- tics differ ...
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PIN CONFIGURATION (TOP VIEW) • 28-pin plastic SOP (375 mil) PD17225GT- , 17226GT- , 17227GT- • 28-pin plastic shrink DIP (400 mil) PD17225CT- , 17226CT- , 17227CT- P0D 2 P0D 3 INT P0E 0 P0E 1 P0E 2 P0E 3 ...
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... I/O port (CMOS push-pull output REM : Remote controller output (CMOS push-pull output) RESET : Reset input V : Power supply DD WDOUT : Hang-up/low voltage detection output (N-ch open-drain output Resonator connection IN OUT 4 PD17225, 17226, 17227, 17228 -5A4, PD17227MC- -5A4, PD17228MC IC2 2 29 P0D 3 28 ...
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BLOCK DIAGRAM P0A 0 P0A 1 P0A P0A 2 P0A 3 P0B 0 P0B 1 P0B P0B 2 P0B 3 P0C 0 P0C 1 P0C P0C 2 P0C 3 PD17225 : 2048 PD17226 : 4096 PD17227 : 6144 P0D PD17228 ...
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... Port 0E (P0E -P0E ) ........................................................................................................................... 0 3 3.6 INT Pin ................................................................................................................................................. 3.7 Switching Bit I/O ................................................................................................................................ 3.8 Specifying Pull-up Resistor Connection ......................................................................................... 4. CLOCK GENERATOR CIRCUIT .................................................................................................. 4.1 Instruction Execution Time (CPU Clock) Selection ........................................................................ 5. 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR CIRCUIT ..................... 5.1 Configuration of 8-bit Timer (with modulo function) ..................................................................... 5.2 Function of 8-bit Timer (with modulo function) ...
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... Reset by Reset Signal Input ............................................................................................................. 9.2 Reset by Watchdog Timer (Connect RESET and WDOUT pins) ................................................... 9.3 Reset by Stack Pointer (Connect RESET and WDOUT pins) ........................................................ 10. LOW-VOLTAGE DETECTOR CIRCUIT (CONNECT RESET AND WDOUT PINS) .................... 11. ASSEMBLER RESERVED WORDS ............................................................................................. 11.1 Mask Option Directives ..................................................................................................................... 11.2 Reserved Symbols ............................................................................................................................. ...
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... Outputs transfer signal for infrared remote controller. 8 (8) REM Active-high output. System reset input. CPU can be reset when low-level signal is input to this pin. While low-level signal is input, oscillator is 13 (13) RESET stopped. Can be connected to pull-up resistor by mask option. 9 (9) V Power supply DD 12 (12) GND Ground ...
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Input/Output Circuits The equivalent input/output circuit for each PD17225 pin is shown below. (1) P0A, P0B V DD Input buffer (2) P0C, P0D Output data latch (3) P0E Pull-up data register Output data latch output disable Selector Input buffer ...
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... WDOUT IC1, IC2 10 PD17225, 17226, 17227, 17228 Recommended Connection Connect Connect Connect to GND. Connect to GND. Input : Individually connect GND via resistor. DD Output : Leave open. Leave open. Connect to GND. Connect to V via resistor. DD These pins cannot be used. Leave open. Data Sheet U12643EJ2V0DS00 ...
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MEMORY SPACE 2.1 Program Counter (PC) The program counter (PC) specifies an address of the program memory (ROM). The program counter is an 11/12/13-bit binary counter as shown in Figure 2-1. Its contents are initialized to address 0000H at ...
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Figure 2-2. Program Memory Map Address 16 bits Reset start address Basic interval timer interrupt vector External input (INT) interrupt vector ...
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Stack A stack is a register to save a program return address and the contents of system registers (to be described later) when a subroutine is called or when an interrupt is accepted. 2.3.1 Stack configuration Figure 2-3 shows ...
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Function of stack The address stack register stores a return address when the subroutine call instruction or table reference instruction (first instruction cycle) is executed or when an interrupt is accepted. It also stores the contents of the address ...
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Data Memory (RAM) Data memory (random access memory) stores data for operations and control. It can be read-/write-accessed by instructions. 2.4.1 Memory configuration Figure 2-4 shows the configuration of the data memory (RAM). The data memory consists of two ...
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General-purpose data memory The general-purpose data memory area is an area of the data memory excluding the system register area, and the port register area. This memory area has a total of 223 nibbles (111 nibbles in BANK0 and ...
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System registers (SYSREG) The system registers are registers that are directly related to control of the CPU. These registers are mapped to addresses 74H-7FH on the data memory and can be referenced regardless of bank specification. The system registers ...
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General register (GR) A general register is a 16-word register on the data memory and used for arithmetic operations and transfer of data to and from the data memory. (1) Configuration of general register Figure 2-6 shows the configuration ...
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Data buffer (DBF) The data buffer on the addresses 0CH to 0FH of data memory is used for data transfer to and from peripheral hardware and for storage of data during table reference. (1) Functions of the data buffer ...
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Table 2-2. Relations between Hardware Peripherals and Data Buffer Hardware Peripherals Name 8-Bit Timer 8-bit counter 8-bit modulo register Remote Controller NRZ low-level Carrier Generator timer modulo register NRZ high-level timer modulo register Address Register Address register Notes 1. In ...
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Note on using data buffer When transferring data to/from the peripheral hardware via the data buffer, the unused peripheral addresses, write-only peripheral registers (only when executing PUT), and read-only peripheral registers (only when executing GET) must be handled as ...
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Register File (RF) The register file mainly consists of registers that set the conditions of the peripheral hardware. These registers can be controlled by dedicated instructions PEEK and POKE, and the embedded macro instructions of RA17K, SETn, CLRn, and ...
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Control registers The control registers consists of a total of 64 nibbles ( bits) of the addresses 00H-3FH of the register file. Of these, however, only 14 nibbles are actually used. The remaining 50 nibbles are unused ...
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Symbol definition of register file An error occurs if a register file address is directly specified as a numeral by the operand “rf” of the “PEEK WR, rf” or “POKE rf, WR” instruction if the 17K Series Assembler (RA17K) ...
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... Connection of a pull-up resistor can be specified in 1-bit units by the P0EBPU (address 17H) of the register file. (When the pull-up resistor is connected, note that the pull-up resistor is not disconnected even when the output mode is set.) On reset, this port functions as an input port ...
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INT Pin This pin inputs an external interrupt request signal. At either the rising or falling edge of the signal input to this pin, the IRQ flag (RF: address 3EH, bit 0) is set. The status of this pin ...
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Switching Bit I/O The I/O which can be set in the input or output mode in bit units is called a bit I/O. P0E is a bit I/O port, which can be set in the input or output mode ...
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... Specifying Pull-up Resistor Connection Whether or not a pull-up resistor is connected to port P0E can be specified by the following registers of the register file in 1-bit units when the port is in the input mode P0EBPU3 P0EBPU2 P0EBPU1 P0EBPU0 Note To disconnect the pull-up resistor in the output mode, clear the corresponding bit of the P0EBPU register. ...
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CLOCK GENERATOR CIRCUIT 4.1 Instruction Execution Time (CPU Clock) Selection The PD17225 is equipped with a clock oscillator that supplies clocks to the CPU and hardware peripherals. Instruction execution time can be changed in two steps (ordinary mode and ...
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TIMER AND REMOTE CONTROLLER CARRIER GENERATOR CIRCUIT The PD17225 is equipped with the 8-bit timer which is mainly used to generate the leader pulse of the remote controller signal, and to output codes. 5.1 Configuration of 8-bit Timer ...
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Figure 5-1. Configuration of 8-bit Timer and Remote Controller Carrier Generator Circuit TMEN TMRES /256 X Selector 7-bit counter X Comparator bit 7 7-bit modulo register NRZLTMM ...
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Function of 8-bit Timer (with modulo function TMEN TMRES TMCK1 TMCK0 Notes 1. When the STOP mode is released, bit 3 must be set. 2. Bit write-only bit. NRZLTMM ...
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Carrier Generator Circuit for Remote Controller PD17225 is provided with a carrier generator circuit for the remote controller. The remote controller carrier generator circuit consists of a 7-bit counter, NRZ high-level timer modulo register (NRZHTMM), and NRZ low-level timer ...
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When bit 7 of NRZLTMM is 0 (carrier output) NRZ REM MAX. 500 ns (delay Note Value when (TMCK1, TMCK0) When (TMCK1, TMCK0) = (1, 1), the value differs depending on how NRZ is manipulated. If NRZ is ...
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Setting carrier frequency and duty factor Where the system clock frequency is f (division ratio /( divided into m:n and is set in the modulo registers as follows: High-level period set value = ...
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... To prevent data from changing, do not execute an interrupt that requires read/write processing and stack, such as key scan interrupt, and the CALL/RET instruction, while the carrier is output. <5> To improve the reliability in case of program hang-up, use the watchdog timer (connect the WDOUT and RESET pins). ...
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BASIC INTERVAL TIMER/WATCHDOG TIMER The basic interval timer has a function to generate the interval timer interrupt signal and watchdog timer reset signal. 6.1 Source Clock for Basic Interval Timer The system clock ( divided, to generate ...
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WDTRES BTMCK BTMRES Note Bits 1 and 3 are write-only bits. 38 PD17225, 17226, 17227, 17228 0 Address On reset R/W Note 03H 0H R/W BTMRES Basic Interval Timer Reset 0 Data read out ...
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... Operation Timing for Watchdog Timer The basic interval timer can be used as a watchdog timer. Unless the watchdog timer is reset within a fixed time is reset therefore necessary to reset through programming the watchdog timer with in a fixed time. The watchdog timer can be reset by setting WDTRES to 1. Note Fixed time: approx ...
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INTERRUPT FUNCTIONS 7.1 Interrupt Sources PD17225 is provided with three interrupt sources. When an interrupt has been accepted, the program execution automatically branches to a predetermined address, which is called a vector address. A vector address is assigned to ...
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Hardware of Interrupt Control Circuit This section describes the flags of the interrupt control circuit. (1) Interrupt request flag and interrupt enable flag The interrupt request flag (IRQ cleared to 0 when the interrupt processing is excuted. An interrupt ...
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IEG This pin selects the interrupt edge to be detected on the INT pin. When this flag is “0”, the interrupt is detected at the rising edge; when it is “1”, the interrupt is detected at the falling edge. ...
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IRQ This is an interrupt request flag that indicates the interrupt request status. When an interrupt request is generated, this flag is set to “1”. When the interrupt has been accepted, the interrupt request flag is reset to “0”. ...
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Interrupt Sequence If IRQ flag is set to “1” when IP flag is “1”, interrupt processing is started after the instruction cycle of the instruction executed when IRQ flag was set has ended. Since the MOVT instruction, EI instruction, ...
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Returning from interrupt processing routine To return from an interrupt processing routine, use the RETI instruction. Then the following processing is executed within an instruction cycle. To enable an interrupt after the processing of an interrupt has been finished, ...
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STANDBY FUNCTIONS PD17225 is provided with HALT and STOP modes as standby functions. By using the standby function, current consumption can be reduced. In the HALT mode, the program is not executed, but the system clock f tained, until ...
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Table 8-2. Operations After HALT Mode Release (2/2) (b) HALT 02H HALT Mode Released by: Interrupt Status 8-Bit Timer 8.2 HALT Instruction Execution Conditions The HALT instruction can be executed, only under special conditions, as shown in Table 8-3, to ...
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STOP Mode In the STOP mode, the system clock (f X consumption. To set the STOP mode, use the STOP instruction. The STOP mode releasing condition can be specified by the STOP instruction operand, as shown in Table 8-4. ...
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STOP Instruction Execution Conditions The STOP instruction can be executed, only under special conditions, as shown in Table 8-5, to prevent the program from hang-up. If the conditions in Table 8-5 are not satisfied, the STOP instruction is treated ...
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... Operation mode or standby mode 9.2 Reset by Watchdog Timer (Connect RESET and WDOUT pins) When the watchdog timer operates during program execution, a low level is output to the WDOUT pin, and the program counter is reset the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0H. ...
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... Reset by Stack Pointer (Connect RESET and WDOUT pins) When the value of the stack pointer reaches during program execution, a low level is output to the WDOUT pin, and the program counter is reset the nesting level of the interrupt or subroutine call exceeds 5 (stack over flow the return instruction is executed without correspondence between CALL and return (RET) instructions established, then regardless of a stack level of 0 (stack underflow), the program can be restarted from address 0H ...
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... Note that some oscillators stop oscillating before the reset function is effected. The low-voltage detector circuit can be set arbitrarily by the mask option. Caution Connect a capacitor to the RESET pin as shown below to stabilize the operation. Remark In this figure, the RESET pin is connected to a pull-up resistor by the mask option. 52 PD17225, 17226, 17227, 17228 = 1 ...
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ASSEMBLER RESERVED WORDS 11.1 Mask Option Directives When developing the PD17225 program, mask options must be specified by using mask option directives in the program. The RESET pin for PD17225 requires a mask option to be specified. 11.1.1 OPTION ...
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Table 11-1. Mask Option Definition Directives Name Directive Operands 1st Operand RESET OPTRES 1 Mask option of RESET PULLUP (w/pull-up resistor) OPEN (w/o pull-up resistor) POC OPTPOC 1 USEPOC (low-voltage detector circuit provided) NOUSEPOC (low-voltage detector circuit not provided) 11.2 ...
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Table 11-2. Reserved Symbols (1/2) Symbol Name Attribute Value DBF3 MEM 0.0CH DBF2 MEM 0.0DH DBF1 MEM 0.0EH DBF0 MEM 0.0FH AR3 MEM 0.74H AR2 MEM 0.75H AR1 MEM 0.76H AR0 MEM 0.77H WR MEM 0.78H BANK MEM 0.79H IXH ...
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Table 11-2. Reserved Symbols (2/2) Symbol Name Attribute Value P0E0 FLG 0.6FH.0 P0E1 FLG 0.6FH.1 P0E2 FLG 0.6FH.2 P0E3 FLG 0.6FH.3 SP MEM 0.81H SYSCK FLG 0.82H.0 WDTRES FLG 0.83H.3 BTMCK FLG 0.83H.2 BTMRES FLG 0.83H.1 INT FLG 0.8FH.0 NRZBF ...
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PD17225, 17226, 17227, 17228 Data Sheet U12643EJ2V0DS00 57 ...
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Column 0 Address Row Address Bit 3 Bit Bit 1 Bit 0 Bit 3 0 Bit Bit 1 0 Bit 0 NRZBF Bit 3 Bit 2 2 Bit 1 Bit 0 Bit 3 Bit ...
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Figure 11-1. Register Files (2/2) Column Address Row Address Bit 3 Bit 2 0 Bit 1 Bit 0 Bit 3 Bit 2 1 Bit 1 Bit 0 Bit 3 Bit 2 2 Bit 1 Bit 0 Bit ...
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INSTRUCTION SET 12.1 Instruction Set Outline BIN. HEX ADD SUB ADDC SUBC 0 ...
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Legend AR : Address register ASR : Address stack register specified by stack pointer addr : Program memory address (low-order 11 bits) BANK : Bank register CMP : Compare register CY : Carry flag DBF : Data buffer h ...
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List of Instruction Sets Group Mnemonic Operand r, m (r) ADD m, #n4 ( (r) Addition ADDC m, #n4 ( INC (r) SUB m, #n4 (m) Subtraction r, m (r) SUBC ...
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Group Mnemonic Operand PUSH AR SP POP AR AR PEEK WR Transfer POKE rf, WR (rf) GET DBF, p (DBF) PUT p, DBF (p) addr Note Branch BR @AR PC addr SP PC CALL @AR SP Subroutine PC ...
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PD17228 Operand addr 12.4 Assembler (RA17K) Built-In Macro Instruction Legend flag n : FLG type symbol n : Bit number < > : Contents in < > can be omitted Mnemonic Operand Built-in SKTn flag ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Item Symbol Supply Voltage V DD Input Voltage V I Output Voltage V O Note High-Level Output Current I OH Note Low-Level Output Current I OL Operating Temperature T ...
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... V lasts for longer. Program hang-up does not occur even DD if the voltage drops, until the reset function is effected (when the RESET pin and WDOUT pin are connected). Some oscillators stop oscillating before the reset function is effected. (MH 0.4 Remark The region indicated by the broken line in the above figure is the guaranteed operating range in the high- speed mode ...
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... IN OUT Notes 1. The oscillation frequency only indicates the oscillator characteristics. 2. The oscillation stabilization time is necessary for oscillation to be stabilized, after V STOP mode release. Caution To use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: • ...
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... Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency necessary to set the oscillation frequency of the resonator in the application circuit. For this necessary to directly contact the manufacturer of the resonator being used ...
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DC Characteristics (T = – Item Symbol High-Level Input Voltage V IH1 V IH2 Low-Level Input Voltage V IL1 V IL2 V IL3 High-Level Input Leakage I LIH Current Low-Level Input Leakage I LIL1 Current ...
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... RSL Note The CPU clock cycle time (instruction execution time) is determined by the oscillation frequency of the reso- nator connected and SYSCK (RF: address 02H) of the register file. The figure on the right shows the CPU clock cycle time t vs. supply voltage V characteristics (refer to 4. ...
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... P0E 3 7 REM OUT 10 4 MHz GND 12 RESET 13 WDOUT 14 Remark The RESET pin can be connected to a pull-up resistor by the mask option. PD17225, 17226, 17227, 17228 P0D 1 28 P0D 0 27 P0C 3 26 P0C 2 25 P0C 1 24 P0C 0 23 P0B 3 22 P0B ...
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PACKAGE DRAWINGS 28 PIN PLASTIC SHRINK DIP (400 mil NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to ...
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PLASTIC SOP (375 mil NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. PD17225, 17226, 17227, 17228 15 detail of ...
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PIN PLASTIC SSOP (300 mil NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 74 PD17225, 17226, 17227, 17228 16 detail of ...
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... For the PD17225 soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document "Semiconductor Device Mounting Technology Manual" (C10535E). For other soldering methods, please consult with NEC personnel. Table 16-1. Soldering Conditions of Surface Mount Type (1) ...
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... Data Memory 223 Pull-Up Resistor of RESET Pin Provided Note Low-Voltage Detector Circuit Provided V Pin, Operation Mode Select Pin Provided PP Handling of WDOUT Pin When Not Used Connect to GND Instruction Execution Time ( 3 2 2 Operation When P0C, P0D Are Standby ...
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PD17225, 17226, 17227, 17228 Data Sheet U12643EJ2V0DS00 77 ...
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APPENDIX B. FUNCTIONAL COMPARISON OF Product Name PD17201A Item ROM Capacity (Bit) 3072 RAM Capacity (Bit) LCD Controller/Driver 136 segments max. Infrared Remote Controller LED output is high-active LED output Carrier Generator (REM) I/O Ports External Interrupt (INT) (rising-edge detection) ...
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PD17225 PD17226 PD17227 PD17228 2048 16 4096 16 6144 16 8192 111 4 223 4 Not provided Provided (without LED output) 20 pins 1 pin (rising edge, falling edge detection) Not provided 2 channels 8-bit timer Basic interval timer Provided ...
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... EV-9500GT-28 Emulation Probe EP-17K30GS is an emulation probe for 17K series 30-pin shrink SOP (300 mil) (under (EP-17K30GS) development). Conversion Adapter EV-9500GT- conversion adapter for 28-pin SOP (375 mil) and is used to connect Note 2 (EV-9500GT-28 ) EP-17K28GT to the target system. PROM Programmer AF-9703, AF-9704, AF-9705, and AF-9706 are PROM programmers corresponding to PD17P218. ...
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Software Name Outline 17K Assembler The RA17K is an assembler com- (RA17K) mon to the 17K series products. When developing the program of devices, RA17K is used in combination with a device file (AS17225). 17K Series The emlC-17K is a ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • ...
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... PC/ trademark of IBM Corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version ...