HFA3861BIN96 Intersil Corporation, HFA3861BIN96 Datasheet
HFA3861BIN96
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HFA3861BIN96 Summary of contents
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... The HFA3861B is housed in a thin plastic quad flat package (TQFP) suitable for PCMCIA board applications. Ordering Information TEMP. o PART NUMBER RANGE ( C) PACKAGE HFA3861BIN - TQFP HFA3861BIN96 - Tape and Reel Pinout GNDd DDD SD 3 SCLK ...
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Typical Application Diagram AntSel HFA3683A RF/IF CONV (FILE# 4634) PLL RF LO REF IN HFA3963 RFPA (FILE# 4635) 44MHz MCLK T/Rsw DIFFERENTIAL SIGNALS For additional information on the PRISM® chip set, visit our web site www.intersil.com or call 1-888-INTERSIL or ...
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Pin Descriptions NAME PIN TYPE I/O V (Analog) 12, 17, 22, Power DC power supply 2.7V - 3.6V (Not Hard wired Together On Chip). DDA 31 V (Digital 37, 57 Power DC power supply 2.7 - 3.6V. DDD ...
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Pin Descriptions (Continued) NAME PIN TYPE I/O MD_RDY 54 O MD_RDY is an output signal to the network processor, indicating header data and a data packet are ready to be transferred to the processor. MD_RDY is an active high signal ...
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HFA3861B AGC RXI ANALOG TXI RXQ INPUTS TXQ AGC TXD A/D V REF TXCLK REFERENCE I REF TX_RDY RXD TX_PE POWER RXC DOWN RX_PE MD_RDY SIGNALS RESET TEST TEST PORT SCLK R/W ANT_SEL SDI FIGURE 1. EXTERNAL ...
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TX Port The transmit data port accepts the data that needs to be transmitted serially from an external data source. The data is modulated and transmitted as soon received from the external data source. The serial data ...
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RXCLK is an output from the HFA3861B and is the clock for the serial demodulated data on RXD. MD_RDY is an output from the HFA3861B and it may be set to go active after the SFD or CRC fields. Note ...
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Power Down Modes The power consumption modes of the HFA3861B are controlled by the following control signals. Receiver Power Enable (RX_PE, pin 61), which disables the receiver when inactive. Transmitter Power Enable (TX_PE, pin 62), which disables the transmitter when ...
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DSSS BPSK 1Mbps BARKER DATA 1 BIT ENCODED TO ONE OF 2 CODE WORDS (TRUE-INVERSE) I OUT Q OUT 11 CHIPS CHIP 11 MC/S RATE SYMBOL 1 MS/S RATE For the 1 and 2Mbps modes, the ...
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Start Frame Delimiter (SFD) Field (16 Bits) - This field is used to establish the link frame timing. The HFA3861B will not declare a valid data packet, even acquires, unless it detects the SFD. The HFA3861B receiver ...
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Scrambling is done by a division using a prescribed polynomial as shown in Figure 9. A shift register holds the last quotient and the output is the exclusive-or of the data and the sum of taps in the shift register. ...
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For the 5.5Mbps CCK mode, the output of the scrambler is partitioned into nibbles. The first two bits are encoded as differential modulation in accordance with Table 5 . All odd numbered symbols of the short Header or MPDU are ...
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A SQ1 evaluation occurs whenever the AGC has remained locked for the entire data ingest period, when this happens, SQ1 is updated between 8 and 9µs into the 10µs dwell. If CS1 is not active, two consecutive SQ1’s are required ...
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The baseband processor uses time invariant correlation to strip the PN spreading and phase processing to demodulate the resulting signals in the header and DBPSK/DQPSK demodulation modes. These operations are illustrated in Figure 13 which is an overall block diagram ...
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V (ANALOG) DD (12, 17, 22, 31) I (21) REF V (16) REF 6-BIT TX_AGC_IN (18) ADC CONTROL 6-BIT TX_IF_AGC (35) DAC ANTSEL (39) ANTSEL (40) REGISTER TIMING GENERATOR MCLK (62) TX_PE FIGURE 11. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION PN ...
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Data Demodulation and Tracking Description (DBPSK and DQPSK Modes) The signal is demodulated from the correlation peaks tracked by the symbol timing ...
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V (ANALOG) DD (12, 17, 22, 31) RX_IF_DET (19) RX_IF_AGC (34) AGC CONTROL 6-BIT RX-RF-AGC (38) DAC 6-BIT RXI (10, 11) A/D 6 6-BIT RXQ (13, 14) A/D 6 ANTSEL (40) ANTENNA SWITCH ANTSEL (39) CONTROL TIMING GENERATOR MCLK (63) ...
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Data Demodulation in the CCK Modes In this mode, the demodulator uses Complementary Code Keying (CCK) modulation for the two highest data rates slaved to the low rate processor which it depends on for acquisition of initial timing ...
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Eb/ BER 2.0 BER 1.0 THY 1, 2 FIGURE 14. BER vs Eb/N0 PERFORMANCE FOR PSK MODES Clock Offset Tracking Performance The PRISM baseband processor is designed to accept data clock offsets ...
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A Default Register Configuration The registers in the HFA3861B are addressed with 7-bit numbers where the lower 1 bit of an 8-bit hexadecimal address is left as unused. This results in the addresses being in increments shown ...
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TABLE 9. CONTROL REGISTER VALUES FOR DUAL ANTENNA DIVERSITY (Continued) CONFIGURATION REGISTER CR40 Threshold for antenna decision CR41 Preamble tracking loop lead coefficient CR42 Preamble tracking loop lag coefficient CR43 Header tracking loop lead coefficient CR44 Header tracking loop lag ...
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Control Registers The following tables describe the function of each control register along with the associated bits in each control register. CONFIGURATION REGISTER 0 ADDRESS (0h) R PART/VERSION CODE Bit 7:4 Part Code 0001 = HFA3861B series Bit 3:0 Version ...
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CONFIGURATION REGISTER 5 ADDRESS (0Ah) R/W TX SIGNAL FIELD Bits 7:4 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bits 3 Select preamble mode 0 = Normal, long preamble interoperable with ...
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CONFIGURATION REGISTER 10 ADDRESS (14h) R/W RX CONFIGURE (Continued) Bits 5:4 SFD Time-out values 00 = 56µ 64µ 128µ 144µs Bit 3 MD_RDY control 0 = After CRC16 1 = After SFD Bit 2 ...
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CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1 (Continued) Bit 1 I A/D clock 0 = enable 1 = disable Bit 0 Q A/D clock 0 = enable 1 = disable CONFIGURATION REGISTER 13 ADDRESS (1Ah) R/W A/D ...
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CONFIGURATION REGISTER 15 ADDRESS (1Eh) R/W AGC GAIN CLIP Bit 7 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bits 6:0 AGC gain clip (7-bit value, 0-127) this is the attenuator ...
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CONFIGURATION REGISTER 25 ADDRESS (32h) R/W AGC RX_IF AND RF Bits 7 AGC RX_RF, This input drives the RX-RF control if AGC override Enable is set to 1 When Polarity bit (CR26[6]) is zero removes 30dB pad 0 ...
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CONFIGURATION REGISTER 31 ADDRESS (3Eh) MANUAL TX POWER CONTROL Bits 7:1 7 bits to DAC input, - range Bit 0 unused CONFIGURATION REGISTER 32 ADDRESS (40h) R/W TEST MODES 1 Bit 7 Selection bit for DAC input test ...
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CONFIGURATION REGISTER ADDRESS 34 (44h) R/W TEST BUS ADDRESS Bits 7:0 address bits for various tests. See Tech Brief #TBD for a description of the factory test modes CONFIGURATION REGISTER ADDRESS 35 (46h) R/W CMF COEFFICIENT CONTROL THRESHOLD Bit 7 ...
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CONFIGURATION REGISTER ADDRESS 41 (52h) R/W PREAMBLE LEAD COEFFICIENT Bit 7:6 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bit 5:0 Preamble Lead Coefficient (0-4 range) (000000 - 100000) CONFIGURATION REGISTER ...
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CONFIGURATION REGISTER ADDRESS 53 (6Ah) R RECEIVED SERVICE FIELD Bit 7:0 a: MSB unused, AGCerror [6:0] range -64 to 63, no fractional bits b: 8-bit value of received service field CONFIGURATION REGISTER ADDRESS 54 (6Ch) R RECEIVED LENGTH FIELD, LOW ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications V = 3.0V to 3.3V CC PARAMETER TX_CLK to TX_PE Inactive (11Mbps) TX_RDY Inactive to Last Chip of MPDU Out TXD Modulation Extension RX_PE Inactive Width RX_CLK Period (11Mbps Mode) RX_CLK Width Hi or Low (11Mbps Mode) ...
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I and Q A/D AC Electrical Specifications PARAMETER Full Scale Input Voltage (V ) P-P Input Bandwidth (-0.5dB) Input Capacitance Input Impedance (DC) FS (Sampling Frequency) NOTE: 21. Not tested, but characterized at initial design and at major process/design changes. ...
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Waveforms (Continued) TX_PE OUT OUT TXRDY TX_CLK TXD RX_PE t RLP MD_RDY RX_CLK t CCA RXD CCA, RSSI NOTE: RXD, MD_RDY is output two MCLK after RXCLK rising to provide ...
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