SC26C94C1A NXP Semiconductors, SC26C94C1A Datasheet
SC26C94C1A
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SC26C94C1A Summary of contents
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... COMMERCIAL INDUSTRIAL V = +5V +10 +5V +10 + – + SC26C94C1N SC26C94A1N SC26C94C1A SC26C94A1A 1 Product specification SC26C94 DACKN IACKN RQN I/O0a–d I/O1a–d I/O2a–d I/O3a–d TDa-d SD00158 DWG # DWG # o C SOT240-1 SOT238-3 853-1471 15179 ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) PIN CONFIGURATIONS 48-Pin Dual-In-Line Package 1 48 X1/CLK 2 47 TXDD 3 46 RXDD 4 45 IRQN ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) BLOCK DIAGRAM 8 BUS BUFFER D0–D7 OPERATION CONTROL RDN WRN ADDRESS DECODE CEN 6 A0–A5 R/W CONTROL RESET DACKN TIMING 2 CRYSTAL X1/CLK OSCILLATOR POWER UP-DOWN X2 LOGIC BAUD RATE GENERATOR DUART CD ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) PIN DESCRIPTION MNEMONIC TYPE CEN I Chip Select: Active low input that, in conjunction with RDN or WRN, indicates that the host MPU is trying to access a QUART register. CEN must be ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) 1 Table 1. QUART Registers A5:0 READ (RDN = Low) 000000 Mode Register a (MR0a, MR1a, MR2a) 000001 Status Register a (SRa) 000010 Reserved 000011 Receive Holding Register a (RxFIFOa) 000100 Input Port ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) NOTES: 1. Registers not explicitly reset by hardware reset power up randomly X1/CLK divide by 2 all circuits receive the divided clock except the BRG and change-of-state detectors. FUNCTIONAL BLOCKS The ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Timer Mode In the timer mode a symmetrical square wave is generated whose half period is equal in time to division of the selected counter/timer clock frequency by the 16-bit number loaded in ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) mean five bytes may be loaded; 111 means 7, etc. Eight positions will be indicated by a binary 111 and the FIFO empty bit will be set. Receiver The receiver accepts serial data ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) position, it considers it an address bit and loads that character to the RxFIFO and set the RxRDY bit in the status register. The user would usually set the receiver interrupt to occur ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) The interrupt arbitration logic insures that the interrupt with the numerically largest bid value will be the only source driving the interrupt bus at the end of the arbitration period. The arbitration period ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Interrupt Context The channel number of the winning “bid” is used by the address decoders to provide data from the interrupting UART channel via a set of Global pseudo-registers. The interrupt Global pseudo-registers ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Table 4. Register Bit Formats, Duart ab. [duplicated for Duart cd] Bit 7 Bit 6 Bit 5 MR0 (Mode Register 0) Rx Watchdog RxINT2 bit Timer 0 = off These bits should normally ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Table 2. Register Bit Formats, Duart ab. [duplicated for Duart cd] (continued) Bit 7 Bit 6 Bit 5 ISR (Interrupt Status Register) I/O Port Delta RxRDY/ Change BREAKb FFULLb ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) In the “Block Error” mode the ORing of the error status bits and the presentation of them to the status register takes place as the bytes enter the RxFIFO. This allows an indication ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) finished processing the present character and is ready to search for the start bit of the next character. Table 5. Bit Rate Generator Characteristics Crystal or Clock = 3.6864MHz NORMAL RATE ACTUAL 16X ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Table 6. Baud Rate BRG RATE = LOW CSR[7:4] ACR[ ACR[ 110 134 ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) The selected set of rates is available for use by the receiver and transmitter. ACR[6:4] – Counter/Timer Mode and Clock Source Select This field selects the operating mode of the counter/timer and its ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) ISR[1] – Receiver Ready or FIFO Full Channel a See the description of ISR[5]. The channel ‘a’ receiver operation is the same as channel ‘b’. ISR[0] – Transmitter Ready Channel a See the ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Table 8. Register Bit Formats, I/O Section Bit 7 Bit 6 Bit 5 IPCR (Input Port Change Register ab) The lower four bits replicate the lower four bits of the IPR. The upper ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) I/O Port Control Channel B (IOPCRB) IOPCRb[7:6] IOPCR[xx] IOPCR[xx] Pin Control Bits Pin Control Bits I/O3B 00 = input IPR(7), TxC output OPRab( output TxC 16x 11 = ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Global Interrupt Byte Count (GIBC) 00000 5 The GIBC is not an actual register but simply outputs the interrupting UART’s transmit or receive byte counter value. The count, accurate at the time IACKN ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER SYMBOL PARAMETER V Input low voltage Input high voltage (except X1/CLK) Input high voltage (except X1/CLK Input high voltage (X1/CLK ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) AC ELECTRICAL CHARACTERISTICS SYMBOL SYMBOL FIGURE FIGURE Reset timing t 7 Reset pulse width RES I/O Port timing t 8 I/O input setup time before RDN Low I/O input hold ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) AC ELECTRICAL CHARACTERISTICS 10%, unless otherwise specified. Limits shown as nn/nn refer to Commercial/Industrial temperature range. Single A CC numbers apply to both ranges. NO. NO. ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) AC ELECTRICAL CHARACTERISTICS Commercial/Industrial temperature range. Single numbers apply to both ranges. NO. NO. FIGURE FIGURE CHARACTERISTIC CHARACTERISTIC 1 3 D[7:0] Valid after IACKN Low 2 3 DACKN Low after IACKN Low 3 ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) HOLD EN BYTE COUNTER TRANSMITTER OFFSET CORRECTION LOGIC IACK BYTE COUNT UPDCIR READ GIBC READ CIR READ CICR D7 D6 INTRAN–INTRDN, I/O0a–I/O3d D0–D7, TxDa–TxDh, I/O0a–I/O3d 1995 May 1 INTBUSN7:0 INVERTING LATCHES INTERRUPT TYPE ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) RESET RDN t PS I/O as Input I/O PINS MUST BE STABLE FOR NON-CHANGING BUS DATA DURING THE READ. CEN WRN I/O as Output NOTE: I/O PIN DATA IS NOT LATCHED WRN 1 ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) t CLK t CTC X1/CLK CTCLK RxC TxC 24pF FOR and C2 should be chosen according to the crystal manufacturer’s specification. C1 ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) RxC (1X INPUT) RxD TxD D1 TRANS- MITTER ENABLED TxRDY (SR2) MR0(5: WRN CTSN (I/O0) 2 RTSN (I/O1) CR[7:4] = 1010 NOTES: 1. TIMING SHOWN FOR MR2[4] = ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) RxD D1 D2 RECEIVER ENABLED RxRDY (SR0) D2 FFULL (SR1) RxRDY/ FFULL ISR(1) RDN OVERRUN (SR4) 1 RTS I/O1 I/ (CR[7:4] = 1010) NOTES; 1. TIMING SHOWN ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) INTERRUPT NOTES The following is a brief description of the new QUART “Bidding” interrupt system, interrupt vector and the use of the Global registers. The new features of the QUARTs have been developed ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) through the most significant 6 bits. The result of this is that the channel value does not ’bid’. However the logic is such that other parts of the bid being equal the condition ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) addressed register. The generation of DACKN begins with the start of a bus cycle (Read, Write or Interrupt Acknowledge) and then requires two edges of the X1 clock plus typically 70ns for its ...