sc26c94 NXP Semiconductors, sc26c94 Datasheet

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... COMMERCIAL INDUSTRIAL V = +5V +10 +5V +10 + – + SC26C94C1N SC26C94A1N SC26C94C1A SC26C94A1A 1 Product specification SC26C94 DACKN IACKN RQN I/O0a–d I/O1a–d I/O2a–d I/O3a–d TDa-d SD00158 DWG # DWG # o C SOT240-1 SOT238-3 853-1471 15179 ...

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... I/O1A D2 I/O2A 16 I/O3B I/O0B 17 D1 I/O1B 18 D0 I/O2B 19 RXDA TXDA TXDA 20 RXDA Product specification SC26C94 IRQN 45 RXDD 44 43 TXDD 42 X1/CLK I/O3D RESET 38 TXDC 37 RXDC 36 35 I/O2D ...

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... IMR V SS2 ISR V SS3 V SS4 1995 May 1 INTERNAL DATA BUS DUART AB 8 TIMING CONTROL 18 3 Product specification SC26C94 CHANNEL A 8 BYTE TRANSMIT FIFO TxDA TRANSMIT SHIFT REGISTER 8 BYTE RECEIVE FIFO RxDA RECEIVE SHIFT REGISTER CSR Rx CSR Tx TxDB CHANNEL B ...

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... X1, this pin should be left unconnected Power and grounds: respectively BUS INTERFACE A0-A5 D (7:0) DTACKN IACKN 1995 May 1 NAME AND FUNCTION BLOCK A COUNTER/TIMER BAUD I/O PORT CONTROL RATE GENERATOR UARTS A/B INTERRUPT CONTROL BLOCK B UARTS C/D I/O CONTROL I/O PORT CONTROL Figure 1. Channel Architecture 4 Product specification SC26C94 SD00161 ...

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... Power Down Power Up Disable DACKN Enable DACKN Reserved Interrupt Vector Register (IVR) Update CIR Global Transmit Holding Reg (GTxFIFO) Interrupt Control Register (ICR) BRG Rate low high 2 Set X1/CLK divide by two 2 Set X1/CLK Normal Reserved Test Mode Reserved 5 Product specification SC26C94 ...

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... The value of D(7:0) is ignored. The START command always loads the contents of CTUR, CTLR to the counting registers. The STOP command always resets the ISR(3) bit in the interrupt status register. 6 Product specification SC26C94 ...

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... The break is terminated by a STOP BREAK command or a transmitter reset.. TxFIFO The TxFIFO empty positions are encoded as a three bit number for presentation to the bidding logic. The coding will equal the number of bytes that remain to be filled. That is, a binary number of 101 will 7 Product specification SC26C94 ...

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... The address character is identified by setting its parity bit to 1. The slave stations will usually have their receivers partially enabled as a result of setting MR1[4:3] to 11. When the receiver sees a one in the parity 8 Product specification SC26C94 ...

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... The channel number and interrupt type fields are hardwired. During the “bid arbitration” process all bids from enabled sources are presented, simultaneously internal interrupt bus. The bidding system and formats are discussed in more detail in following sections. 9 Product specification SC26C94 ...

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... The buffers driving the CIR to the DBUS also provide the means of implementing the Global Interrupting Channel and Global Byte Count Registers, described in a later section. The winning bid channel number and interrupt type fields can also be used to generate part of the Interrupt Vector, as defined by the Interrupt Control Register. 10 Product specification SC26C94 ...

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... The operation of the QUART is programmed by writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU. Addressing of the registers is described in Table 1. The bit formats of the QUART registers are depicted in Table 2. 11 Product specification SC26C94 Chan # 2 Chan # 2 SD00163 ...

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... Yes 1 = Yes Overrun Error TxEMT Yes 1 = Yes Delta 0 = off Product specification SC26C94 Bit 1 Bit 0 These bits not implemented Parity Type Bits per Character Stop Bit Length* Transmitter Clock Select See text ...

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... FIFO. In the block mode, the status provided in the SR for these bits is the accumulation (logical-OR) of the status for all characters coming to the top of the FIFO since the last reset error command was issued. 13 Product specification SC26C94 Bit 1 Bit 0 RxRDY/ TxRDYa FFULLa ...

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... MR2[ selects two stop bits to be transmitted. RECEIVER NOTE: In all cases, the receiver only checks for a “mark” condition at the center of the stop bit (1/2 to 9/16 bit time into the stop bit position). At this time the receiver has 14 Product specification SC26C94 ...

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... Wake-up Mode). CR[0] – Enable Receiver Enables operation of the receiver. If not in the special wake-up mode, this also forces the receiver into the search for start bit state. 15 Product specification SC26C94 ACR[ I/O3x – 16X I/O3x – 1X ...

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... This bit selects between two sets of baud rates that are available within each baud rate group generated by the BRG. See Table 3. Set 1: 50, 110, 134.5, 200, 300, 600, 1.05k, 1.2k, 2.4k, 4.8k, 7.2k, 9.6k, and 38.4k baud. Set 2: 75, 110, 150, 300, 600, 1.2k, 1.8k, 2.0k, 2.4k, 4.8k, 9.6k, 19.2k, and 38.4k baud. 16 Product specification SC26C94 TEST ACR[ ACR[ 4,800 7,200 880 880 ...

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... The command, however, does not stop the C/T. ISR[2] – Channel a Change in Break This bit, when set, indicates that the receiver has detected the beginning or the end of a received break reset when the CPU issues a reset break change interrupt command. 17 Product specification SC26C94 ...

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... A change on the pin will be required to be stable for at least 26.04 s and as much as 52.08 s for the COS detectors to confirm a change. Note that changes in the X1/clock frequency will effect this stability requirement. COS detectors are reset by a read of the IPCR. 18 Product specification SC26C94 ...

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... I/O1A IPR(4), RxC in IPR(1), C/Tab Clk in OPRab(4) OPRab( RTSN if IOPCR[5: RTSN if IOPCR[5:4] RxC 1x RxC 16x RxC 16x RxC 1x 19 Product specification SC26C94 Bit 1 Bit 0 I/O1a I/O0a 0 = Low 0 = Low 1 = High 1 = High I/O1c I/O0c 0 = Low 0 = Low 1 = High 1 = High I/O0x CONTROL I/O1c I/O0c ...

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... With Type = x11, the # Bytes field indicates the count of received 2 bytes available for reading, while with Type = x10 it indicates the number of bytes that can be written to the transmit FIFO. The CIR is Read only at address 28H. 20 Product specification SC26C94 IOPCRb[1:0] I/O0B IPR(2), CTSN OPRab(2) 01 TxC 1x ...

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... MSBs are always used, while the less significant bits can be replaced by the interrupt type code and/or Channel code bits contained in the CIR. The IVR is write only at address 29H. IVC 2 21 Product specification SC26C94 State Change C with IVC = 0x w/IVC = ...

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... GND open open TTL input levels 25 C with X1 = 4MHz 22 Product specification SC26C94 LIMITS UNIT UNIT Min Typ Max 0 2.2 0. 0.8V V 0 – – –100 ...

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... PARAMETER With respect to a 3.6864MHz clock on pin X1/CLK 2 active maximum junction temperature. = 50pF 2. Test conditions for rest of outputs minimum test rate is 2.0MHz. CLK 23 Product specification SC26C94 LIMITS UNIT UNIT Min Typ Max 200 110 ns 110 ns ...

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... CEN 3 RDN WRN 6 D[7:0] Figure 2. A Read Cycle Followed by a Write Cycle without DACKN 1995 May 1 1 CHARACTERISTIC CHARACTERISTIC READ CYCLE Product specification SC26C94 LIMITS UNIT UNIT Min Typ Max 110/115 ns 110/115 ...

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... Limits shown as nn/nn refer edges 110/115 5 2 Figure 3. Interrupt Knowledge (IACKN) Timing VALUE FOR THIS INTERRUPT Figure 4. Interrupt Bid Arbitration Timing 25 Product specification SC26C94 LIMITS UNIT UNIT Min Typ Max 110/115 ns 90/122 + edges ...

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... INTRAN–INTRDN, I/O0a–I/O3d D0–D7, TxDa–TxDh, I/O0a–I/O3d 1995 May 1 INTBUSN7:0 INVERTING LATCHES INTERRUPT TYPE Figure 5. Current Interrupt Register Logic 2.7K 60pF 6K 150pF Figure 6. Test Conditions on Outputs 26 Product specification SC26C94 CURRENT CHANNEL INTERRUPT REGISTER D0 SD00167 +5V +5V 1.6K SD00168 ...

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... May 1 t RES Figure 7. Reset Timing OLD DATA Figure 8. I/O Port Timing POINT 0.5V ABOVE V . THIS POINT REPRESENTS NOISE MARGIN THAT AS Figure 9. Interrupt Timing 27 Product specification SC26C94 SD00169 NEW DATA SD00170 V +0. +0. SD00171 ...

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... TYPICAL CRYSTAL SPECIFICATION FREQUENCY: LOAD CAPACITANCE (C L TYPE OF OPERATION: Figure 10. Clock Timing 1 BIT TIME ( CLOCKS t TXD t TCS Figure 11. Transmit Clock Timing 28 Product specification SC26C94 +5V 1K required for TTL gate STANDARD BRG BAUD RATES 38.4kHz CLOCK TO I/O CHANGE-OF-STATE DETECTORS To ...

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... CR[7:4] = 1010 NOTES: 1. TIMING SHOWN FOR MR2[ TIMING SHOWN FOR MR2[ 1995 May RXS RXH Figure 12. Receive Clock Timing D2 D3 BREAK D3 START D4 STOP BREAK BREAK Figure 13. Transmitter Data Timing 29 Product specification SC26C94 SD00174 WILL D6 NOT BE TRANSMITTED CR[7:4] = 1010 SD00175 ...

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... Figure 14. Receiver Data Timing BIT MR1 [ ADD#2 BIT 9 BIT STATUS DATA ADD#1 D0 Figure 15. Wake-Up Mode 30 Product specification SC26C94 D11 D12 D13 D10 RESET BY COMMAND D10 WILL BE OVERWRITTEN BY D11, 12, ETC SD00176 BIT 9 ADD#2 1 BIT 9 ...

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... Note that interrupt threshold value in the ICR is 6 bits long. This value is aligned with the bid arbitration logic such that it bids only 31 Product specification SC26C94 FUNCTION Receiver bid With error Receiver bid No error Transmit bid Receive Break ...

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... During a read of the QUART DACKN signals that valid data is on the data bus. During a write to the QUART DACKN signals that data placed on the bus by the control processor has been written to the 32 Product specification SC26C94 BIT 2 BIT 1 BIT 0 ICR[1:0] Channel number ...

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... QUART) The principles to keep in mind are: 1. When IACKN is not used the CIR should be updated via command DACKN is not used it should be disabled. 3. When in the asynchronous mode be sure DACKN is enabled. 4. With 68xxx type controllers the RDN signal must be generated. 33 Product specification SC26C94 ...