UPD30500S2-150 NEC, UPD30500S2-150 Datasheet
UPD30500S2-150
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UPD30500S2-150 Summary of contents
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... The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12031EJ4V0DS00 (4th edition) ...
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APPLICATIONS • High-performance embedded systems • Multimedia systems • Entry-class computers • Image processing systems ORDERING INFORMATION Part number PD30500RJ-150 223-pin ceramic PGA (48 PD30500RJ-180 223-pin ceramic PGA (48 PD30500RJ-200 223-pin ceramic PGA (48 PD30500S2-150 272-pin plastic BGA (C/D advanced ...
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PIN CONFIGURATION • 223-pin ceramic PGA (48 48) PD30500RJ-150 PD30500RJ-180 PD30500RJ-200 Bottom View PD30500, 30500A, 30500B Top View ...
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No. Name No. Name SysADC6 DD A3 GND C6 SysAD16 SysAD50 DD A5 GND C8 SysAD22 A6 GND C9 SysAD24 A7 V C10 SysAD28 DD A8 GND C11 SysAD62 A9 V C12 SysAD44 DD ...
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BGA (C/D advanced type) (29 PD30500S2-150 PD30500S2-180 PD30500S2-200 PD30500AS2-250 Note PD30500BS2-300 Bottom View Note Under development ...
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PD30500 No. Name No. Name A1 GND C5 ScDCE1 ScDCE0 DD A3 GND C7 ScCWE0 A4 SysAD32 C8 ScTCE A5 GND C9 Modeln A6 ScCWE1 C10 Reserved A7 GND C11 GNDP C12 Reserved ...
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PD30500A, 30500B No. Name No. Name A1 GND C5 ScDCE1 ScDCE0 DD A3 GND C7 ScCWE0 A4 SysAD32 C8 ScTCE A5 GND C9 Modeln A6 ScCWE1 C10 NC A7 GND C11 GNDP ...
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... External Request GND: Ground GNDP: Quiet GND for PLL Int (0:5): Interrupt Request ModeClock: Boot Mode Clock Modeln: Boot Mode Data In NC: No Connection NMI: Non-maskable Interrupt Request RdRdy: Read Ready Release: Release Interface Reset: Reset ScCLR: Secondary Cache Block Clear ScCWE (0:1): ...
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INTERNAL BLOCK DIAGRAM Data, address Control SysClock Clock System interface generator Instruction cache Instruction address Pipeline control PD30500, 30500A, 30500B Data cache CP0 TLB Execution unit Data Sheet U12031EJ4V0DS00 Floating-point unit 9 ...
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PIN FUNCTIONS ................................................................................................................................ 11 2. ELECTRICAL SPECIFICATIONS ...................................................................................................... 13 2.1 PD30500 .................................................................................................................................................... 13 2.2 PD30500A .................................................................................................................................................. 16 2.3 PD30500B (Preliminary) .......................................................................................................................... 19 2.4 Test Condition ............................................................................................................................................ 22 2.5 Timing Chart ............................................................................................................................................... 22 3. PACKAGE DRAWING ........................................................................................................................ 27 4. RECOMMENDED ...
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PIN FUNCTIONS Pin Name I/O SysAD (0:63) I/O System address/data bus. 64-bit bus for communication between processor, secondary cache and external agent. SysADC (0:7) I/O System address/data check bus. 8-bit bus including check bits for the SysAD bus. SysCmd ...
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Pin Name I/O Int (0:5) Input Interrupt. General-purpose processor interrupt requests whose input statuses can be confirmed by bits 15 through 10 of cause register. NMI Input Non-maskable interrupt. Interrupt request that cannot be masked. ColdReset Input Cold reset. Signal ...
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ELECTRICAL SPECIFICATIONS 2.1 PD30500 Absolute Maximum Ratings Parameter Symbol Supply voltage V DD Note Input voltage V I Operating case temperature T C Storage temperature T stg Note The upper limit of the input voltage (V Cautions 1. Do ...
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Capacitance Parameter Symbol Input capacitance C In Output capacitance C out AC Characteristics ( +70 C (PGA Package Clock parameter Parameter Symbol System clock high-level width t CH System clock low-level width t CL Notes ...
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System Interface Parameter Parameter Symbol Data output hold time t DM Data output delay time t DO Data input setup time t DS Data input hold time t DH Boot Mode Interface Parameter Parameter Symbol More data setup time t ...
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PD30500A Absolute Maximum Ratings Parameter Symbol Supply voltage Note Input voltage V I Operating case temperature T C Storage temperature T stg Note The upper limit of the input voltage (V Cautions 1. Do ...
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Power Application Sequence Two kinds of power sources are provided with the V fixed. However, make sure that either of the power supplies does not remain turned on for 1 second or more while the other remains off. Parameter Symbol ...
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System Interface Parameter Parameter Symbol Data output hold time t DM Data output delay time t DO Data input setup time t DS Data input hold time t DH Boot Mode Interface Parameter Parameter Symbol Mode data setup time t ...
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PD30500B (Preliminary) Absolute Maximum Ratings Parameter Symbol Supply voltage Note Input voltage V I Operating case temperature T C Storage temperature T stg Note The upper limit of the input voltage (V Cautions 1. ...
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Capacitance Parameter Symbol Input capacitance C In Output capacitance C out AC Characteristics ( + Clock parameter Parameter Symbol System clock high-level width t CH System clock low-level width t CL Notes 1, 2 ...
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System Interface Parameter Parameter Symbol Data output hold time t DM Data output delay time t DO Data input setup time t DS Data input hold time t DH Boot Mode Interface Parameter Parameter Symbol Mode data setup time t ...
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Test Condition Test point SysClock All output pins Load Conditions All output pins 2.5 Timing Chart Clock timing t CP SysClock 50 PD30500, 30500A, 30500B 50 50% DUT ...
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Mode clock timing t ModeClock 50% Clock jitter SysClock System interface edge timing SysAD (0 : 63), SysADC (0 : 7), SysCmd (0 : 8), SysCmdP, ScLine (0 : 15), ScWord (0 : 1), ScTCE, ScValid ValidOut, Release, ScCLR, ScCWE ...
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Boot mode interface edge timing ModeClock ModeIn Clocking relations Cycle 1 SysClock (Input) PClock (Output SysAD Driven Data (Output) SysAD Received Data (Input Power application sequence (V 5000A 0. ...
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Reset Timing Power-on reset timing V Note 1 DD Note 2 V I/O 3.135 V DD SysClock 100 256 SysClock ModeClock t MDS ModeIn ColdReset Reset Notes 1. 3.135 V (V 5000), 2.375 ...
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Warm reset timing Note SysClock ColdReset Reset Note V 5000A, V 5000B only PD30500, 30500A, 30500B 64 SysClock Data Sheet U12031EJ4V0DS00 ...
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PACKAGE DRAWING 223 PIN CERAMIC PGA A Index Mark NOTE Each lead centerline is located within its true position (T.P.) at maximum material condition. PD30500, 30500A, 30500B ...
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PLASTIC BGA (C/D advanced type) (29x29 Index area PD30500, 30500A, 30500B ...
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... Soldering this product under the following soldering conditions is recommended. For the details of the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and recommended other than those recommended, consult NEC. (1) Soldering Conditions of Surface Mount Type PD30500S2-150: ...
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APPENDIX DIFFERENCES BETWEEN THE V Item Operating frequency Internal External Pipeline Cache Primary instruction cache Primary data cache Secondary cache interface Data protection System bus Write data transfer rate Initialization pin at reset Status after last data write Integer operation ...
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PD30500, 30500A, 30500B Data Sheet U12031EJ4V0DS00 31 ...
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PD30500, 30500A, 30500B Data Sheet U12031EJ4V0DS00 ...
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PD30500, 30500A, 30500B Data Sheet U12031EJ4V0DS00 33 ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • ...
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... Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...