UPC1854AGT-E2 NEC, UPC1854AGT-E2 Datasheet
UPC1854AGT-E2
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UPC1854AGT-E2 Summary of contents
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... For information, please call: (508) 229-2500 (U.S.A.), or (03) 5790-5391 (Tokyo). The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S12816EJ3V0DS00 (3rd edition) ...
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SYSTEM BLOCK DIAGRAM Tuner IF processing DTS interface US MTS processing SDA Tuning microcontroller SCL Remote controller receive amp. PIN photodiode and deflecting Chroma output signal processing Vertical output PC1854A L Surround signal processing R Data Sheet ...
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BLOCK DIAGRAM VRE 2 1 PD1 3 Pilot Discrimination 0.1 F Phase Comparator PD2 4 Stereo 1/4 VCO Stereo + + Phase 4 ...
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PIN CONFIGURATION (Top View) 28-pin plastic SDIP (10.16 mm (400)) • PC1854ACT 28-pin plastic SOP (9.53 mm (375)) • PC1854AGT 1 V Power ( VRE 1/2 V Filter CC 3 PD1 Pilot Discrimination Filter 1 4 PD2 ...
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PIN EQUIVALENT CIRCUITS .............................................................................................................................. 6 2. BLOCK FUNCTIONS .......................................................................................................................................... 13 2.1 Stereo Demodulation Block ..................................................................................................................... 14 2.2 SAP Demodulation Block ........................................................................................................................ 15 2.3 dbx Noise Reduction Block ..................................................................................................................... 16 2.4 Matrix Block .............................................................................................................................................. BUS ...
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PIN EQUIVALENT CIRCUITS Pin No. Pin Name 1 Power ( 1/2 V Filter CC 3 Pilot Discrimination Filter 1 4 Pilot Discrimination Filter 2 6 Symbol Internal Equivalent Circuit V CC VRE ...
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Pin No. Pin Name 5 Phase Comparator Filter 1 6 Phase Comparator Filter 2 7 Composite Signal Input 8 SAP Offset Absorption Symbol Internal Equivalent Circuit COM 1 ...
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Pin No. Pin Name 9 SAP Discrimination Filter 10 Noise Detection Filter 8 Symbol Internal Equivalent Circuit SDT NDT ...
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Pin No. Pin Name 11 SAP Single Output 12 SAP Single Input 13 External SAP Input Symbol Internal Equivalent Circuit SOT 2 k 200 ESA Data Sheet ...
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Pin No. Pin Name 14 Analog GND 2 15 SDA (for I C bus SCL (for I C bus Digital GND (for I C bus) 18 Variable Emphasis Offset Absorption 19 Spectral RMS Offset Absorption Note ...
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Pin No. Pin Name 20 Wide-Band RMS Offset Absorption 21 Timing Current Setting 22 Spectral RMS Timing 23 Wide-Band RMS Timing 24 VCA Offset Absorption Symbol Internal Equivalent Circuit WRB Same as pin 19 ITI ...
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Pin No. Pin Name 25 Normal Output 26 R-channel Output 27 L-channel Output 28 Monaural Offset Absorption 12 Symbol Internal Equivalent Circuit NOT 10 k 200 200 ROT Same as pin 25 LOT MOA ...
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BLOCK FUNCTIONS In the US, TV audio signals are broadcast in FM modulation. The stereo (L–R), Sub Audio Program (SAP) and telemetry signals are multiplexed in a higher frequency band than the monaural (L+R) signal ( ...
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... LPF. The two signals differ from each other by 90 degrees in terms of phase. The resistor and capacitor connected to Pins D1 and D2 form a filter that smooths the phase error signal output from the stereo phase comparator, converting the error signal to the DC voltage. When the voltage ...
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... D4) is set “1”. The sensitivity and time constant of the circuit are adjusted by setting the values of the resistor and capacitor connected to the NDT. (4) SAP detector Detects the signal from the SAP band-pass filter and smooths it through the SDT pin and inputs it to the comparator. When the SAP signal is detected, the SAP signal bit (read register, bit D5) is set “ ...
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Noise Reduction Block All the filters required for TV-dbx noise reduction are incorporated. The response to these filters is adjusted by setting all the Filter setting bits (write register, subaddress 02H, bits D0 to D5). (1) LPF This ...
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... Wide-band RMS Detects the RMS value of the signal passed through the wide-band RMS filter, and converts the signal to the DC voltage. The release time is set by adjusting the current I external capacitor connected to the WTI pin. The current I 2.4 Matrix Block (1) Matrix Adds L+R signal and L–R signal to output L signal, and subtracts L+R signal from L–R signal to output R signal ...
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I C BUS INTERFACE 2 The PC1854A uses the I C bus interface that is developed by Philips. The serial clock line (SCL) and serial data line (SDA) employ the 2-wire configuration as shown in Figure 3-1. The ...
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Data Transfer (1) Start condition The start condition is created when SDA changes from high to low while SCL is high, as shown in Figure 3-2. When the PC1854A receives this information, it captures data sent in synchronization with ...
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Data Transfer Format An example of data transfer in the write mode is shown in Figure 3-4. Figure 3-4. Data Transfer Example in Write Mode Write SDA mode SCL ...
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The format for 1-byte data transfer is the following: Slave Write Acknow Start Subaddress address mode -ledge (2) Continuous data transfer The format when transferring multiple (7) bytes of data at one time is the following: ...
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I C BUS COMMANDS 4.1 Subaddress List (1) Write register (command list) MSB Subaddress 00H 0 During noise detection Stereo/SAP output stop 0: SAP OFF 1: Stereo, SAP OFF 01H 0 f monitor H ON/OFF ...
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... Write “1” to bit D6 (f monitor: ON) of subaddress 01H. H <3> Connect frequency counter to ROT pin, and set bits (Stereo VCO setting bits) of subaddress 01H so that frequency counter displays 15.73 kHz ( 0.1 kHz). <4> When setting is completed, write “0” to bit D6 (f (3) Filter setting (write register, subaddress 02H, bits D6 to D0) < ...
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... Write “1” to bit monitor: ON) of subaddress 05H. H <4> Connect a frequency counter to the ROT pin, and set bits subaddress 05H (SAP VCO setting bits) so that 78.67 kHz ( 0.5 kHz) is displayed on the frequency counter. <5> When setting is completed, write “0” to bit < ...
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Explanation of Write Register (1) Stereo/SAP output stop function during noise detection Stereo/SAP output stop can be selected with the data of bit D6 of subaddress 00H during weak electrical field conditions (noise level during recommended circuit use is ...
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Mode switch (L-, R-channel output (LOT, ROT pins)) The signal to be output can be selected from the L- and R-channel outputs (LOT, ROT pins) with bits subaddress 06H. For the combinations of bit and ...
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Mode switch (normal signal output (NOT pin)) The signal output from the normal signal output (NOT pin) can be selected with bits subaddress 06H. For the combinations of bit and output signal, refer to section ...
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Explanation of Read Register (1) Power-on reset detection Whether a power-on reset was detected is detected with bit D7 of the read register. Figure 4-5. Power-On Reset Detection Broadcast status Power-on Stereo SAP reset pilot signal ...
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Stereo, SAP broadcast reception (reception status) detection Whether SAP or stereo broadcast is being received and the PC1854A outputs the audio signal can be de- tected with bits D2 and D3 of the read register. The register data become ...
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MODE MATRIX 5.1 L-, R-Channel Output (LOT, ROT pins) Matrix Mute OFF (Write register, subaddress 06H, bit D0 : “1”) (1) Read register, bit D4: 0 Broadcast Write Register mode Forced Stereo/SAP SAP1/SAP2 monaural switch switch ON/OFF Subaddress 06H ...
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Normal Output (NOT pin) Matrix Mute OFF (Write register, subaddress 06H, bit D0 : “1”) Broadcast mode Normal track Normal track output select 2 output select 1 Bit: D4 Bit: D5 Monaural — — Stereo — — Monaural 0 ...
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... Remark If the load capacitance of the output pins (SOT, NOT, ROT, LOT pins) exceeds 100 pF, parasitic oscillation may occur. In this case, connect a resistor between the output pins and the load capaci- tance. Bear in mind that the load capacitance is changed by wiring pattern on the printed circuit board ...
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... Reducing the capacitor value increases the capture range, and increasing it reduces the capture range. However, too small a capacitor value may cause the distortion rate to become worse during stereo output, or may cause malfunction. In this case, please contact NEC. Table 6-3. External Components Pin description ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (Unless otherwise specified, T Parameter Symbol Power supply voltage bus input pin voltage Composite signal input voltage Power dissipation Operating ambient temperature Storage temperature Caution If any of the parameters exceeds ...
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Electrical Characteristics (unless otherwise specified, T Parameter Supply current I Stereo detection input sensitivity ST Stereo detection hysteresis ST Stereo detection capture range ST ST SAP detection input sensitivity SAP SAP detection hysteresis SAP Noise detection input sensitivity NO Noise ...
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Parameter SAP single frequency characteristics 1 SAP single frequency characteristics 2 SAP single frequency characteristics 3 Stereo channel separation 1 Stereo channel separation 2 Stereo channel separation 3 Monaural total harmonic distortion Stereo total harmonic distortion 1 Stereo total harmonic ...
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Test Condition Parameters for Electrical Characteristics (Unless otherwise specified Parameter Symbol Supply current Stereo detection input ST ST SENCE sensitivity Stereo detection hysteresis Input signal ...
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Parameter Symbol Stereo total output voltage V OST SAP total output voltage V OSAP1 SAP single output voltage V OSAP2 Normal output voltage V ONO Difference between V OLR monaural L and R output voltage Monaural total frequency V OMO1 ...
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Parameter Symbol Stereo total frequency V V OST3 characteristics 3 V(8k) : Output voltage of LOT pin V(300) : Output voltage of LOT pin Stereo total frequency V V OST4 characteristics 4 V(12k) : Output voltage of LOT pin V(300) ...
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Parameter Symbol Stereo channel separation 1 Sep 1 Stereo channel separation 2 Sep 2 Stereo channel separation 3 Sep 3 Monaural total harmonic THD MO distortion Stereo total harmonic THD ST1 distortion 1 Note For details about the User Mode, ...
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Parameter Symbol Stereo total harmonic THD L-channel ST2 distortion 2 THD R-channel THD SAP total harmonic distortion THD THD SAP1 SAP single harmonic THD THD SAP2 distortion Normal output harmonic THD THD NO distortion Crosstalk 1 (SAP stereo ...
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Parameter Symbol SAP total S/N S/N SAP Normal output S/N S/N NO Total muting level Mute dbx timing current I T Inter-mode DC offset 1 V DOF1 Inter-mode DC offset 2 V DOF2 Inter-mode DC offset 3 V DOF3 Note ...
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Parameter Symbol Inter-mode DC offset DOF4 V V Inter-mode DC offset DOF5 V V Note For details about the User Mode, refer to chapter 5. MODE MATRIX. Test Conditions = V – V DOF4 ...
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MEASURING CIRCUIT 4.7 F Note 1 Multiple Audio Signal Generator 2 0 0.047 0. ...
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PACKAGE DRAWINGS 28-PIN PLASTIC SDIP (10.16mm400 NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. Item "K" to center ...
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PLASTIC SOP (9.53 mm (375 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition detail of lead end ...
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... The PC1854A should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representa- tive. Table 10-1. Surface Mounting Type Soldering Conditions PC1854AGT : 28-pin plastic SOP (9 ...
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... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others ...