UPA1717G-E1 NEC, UPA1717G-E1 Datasheet

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UPA1717G-E1

Manufacturer Part Number
UPA1717G-E1
Description
P-channel enhancement type power MOS FET
Manufacturer
NEC
Datasheet

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Document No.
Date Published
Printed in Japan
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS (T
Remark
DESCRIPTION
Transistor designed for power management
applications of notebook computers.
FEATURES
Drain to Source Voltage (V
Gate to Source Voltage (V
Drain Current (DC)
Drain Current (pulse)
Total Power Dissipation (T
Channel Temperature
Storage Temperature
Notes 1. PW
The PA1717 is P-Channel MOS Field Effect
Low on-state resistance
R
R
Low C
Built-in G-S protection diode
Small and surface mount package (Power SOP8)
DS(on)1
DS(on)2
PART NUMBER
2. Mounted on ceramic substrate of 1200 mm
iss
PA1717G
G14047EJ1V0DS00 (1st edition)
June 2000 NS CP(K)
= 33 m
= 59 m
: C
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
iss
= 830 pF TYP.
10 s, Duty Cycle
MAX. (V
MAX. (V
Note1
DS
A
GS
GS
GS
= 25°C)
= 0 V)
= 0 V)
= 10 V, I
= 4.5 V, I
Power SOP8
P-CHANNEL POWER MOS FET
PACKAGE
Note2
1 %
D
D
A
= 3 A)
= 3 A)
= 25°C, All terminals are connected.)
INDUSTRIAL USE
I
I
D(pulse)
V
V
D(DC)
T
T
P
DSS
GSS
DATA SHEET
stg
ch
T
SWITCHING
2
–55 to +150
x 2.2 mm
MOS FIELD EFFECT TRANSISTOR
#
#
150
2.0
#
30
25
24
6
8
1
°C
°C
5.37 MAX.
W
V
V
A
A
PACKAGE DRAWING (Unit : mm)
0.40
1.27
+0.10
–0.05
0.78 MAX.
5
4
0.12 M
EQUIVALENT CIRCUIT
Gate
Gate
Protection
Diode
1,2,3
4
5,6,7,8
0.5 ±0.2
©
6.0 ±0.3
PA1717
4.4
; Source
; Gate
; Drain
Source
Drain
Body
Diode
1999, 2000
0.8
0.10

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UPA1717G-E1 Summary of contents

Page 1

... Duty Cycle 2. Mounted on ceramic substrate of 1200 mm Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. ...

Page 2

... Reverse Recovery Charge TEST CIRCUIT 1 SWITCHING TIME D.U. Wave Form Wave Form = 1 s Duty Cycle °C, All terminals are connected.) A SYMBOL TEST CONDITIONS DS(on 4 DS(on GS(off) DS ...

Page 3

TYPICAL CHARACTERISTICS (T A DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 100 120 140 160 T - Ambient Temperature - ˚C A FORWARD BIAS SAFE OPERATING AREA 100 I ...

Page 4

FORWARD TRANSFER CHARACTERISTICS 100 150˚C A 75˚C 25˚C 1 25˚C 0.1 0.01 0.001 Gate to Source Voltage - V GS FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT 100 ...

Page 5

DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE 80 Pulsed 100 150 T - Channel Temperature - ˚C ch CAPACITANCE vs. ...

Page 6

Data Sheet G14047EJ1V0DS00 PA1717 ...

Page 7

Data Sheet G14047EJ1V0DS00 PA1717 7 ...

Page 8

... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others ...

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