UPD705101GM-100-8ED NEC, UPD705101GM-100-8ED Datasheet
UPD705101GM-100-8ED
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UPD705101GM-100-8ED Summary of contents
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DESCRIPTION The PD70501 (V831 32-bit RISC microprocessor for embedded control applications, with a high-performance TM 32-bit V830 processor core and many peripheral functions such as a DRAM/ROM controller, 4-channel DMA controller, real-time pulse unit, serial interface, and interrupt ...
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ORDERING INFORMATION Part Number PD705101GM-100-8ED PIN CONFIGURATION (TOP VIEW) • 160-pin plastic LQFP (fine pitch) (24 PD705101GM-100-8ED GND GND ...
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PIN NAMES A1-A23 : Address Bus BCYST : Bus Cycle Start BT16B : Boot Bus Size 16 bit CLKOUT : Clock Out CS1-CS7 : Chip Select D0-D31 : Data Bus DCK : Debug Clock DDI : Debug Data Input DDO ...
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BLOCK DIAGRAM DCK DMS DDI DCU DDO TRCDATA0 - TRCDATA3 DRST CLKOUT RESET SYU NMI TI, TCLR INTP10/TO10, RPU INTP12/TO11 INTP11, INTP13 ICU INTP00 - INTP03 P10 PORT0/SCLK PORT1/SO CSI PORT2/SI TXD RXD 4 IOWR IORD UUMWR, ...
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PIN FUNCTIONS LIST ......................................................................................................................... 6 2. INTERNAL UNITS ................................................................................................................................ 8 3. CPU FUNCTION ................................................................................................................................. 10 4. INTERRUPT/EXCEPTION PROCESSING FUNCTION ..................................................................... 11 5. BUS CONTROL FUNCTION .............................................................................................................. 13 6. WAIT CONTROL FUNCTION ............................................................................................................. 13 7. MEMORY ACCESS CONTROL FUNCTION ...................................................................................... ...
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PIN FUNCTIONS LIST Pin Name I/O D0-D31 3-state I/O Data bus A1-A23 3-state output Address bus UUCAS Column address strobe (most significant byte) ULCAS Column address strobe (most significant byte) LUCAS Column address strobe (third byte) LLCAS Column address ...
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... NMI Input Non-maskable interrupt request RESET System reset PORT0 I/O Port PORT1 PORT2 X1 – Connects crystal resonator. (Opened when external clock is input.) X2 Input Connects crystal resonator or inputs external clock. CLKOUT Output Bus clock output DCK Input Debug clock input DDI Debug data input ...
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... Clock generator (CG) A frequency three times higher than that of an oscillator connected to the X1 and X2 pins is supplied as the operating clock of the CPU. In addition, a bus clock (with the same cycle as the input clock) is also supplied as the operating clock of the peripheral units ...
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System control unit (SYU) A circuit that rejects noise on the RESET signal (input)/NMI signal (input) is provided. (9) Debug control unit (DCU) A circuit to realize mapping and trace functions is provided to implement basic debugging functions. PD705101 ...
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CPU FUNCTION The features of the CPU function are as follows: • High-performance 32-bit architecture for embedded control applications • Cache memory Instruction cache : 4K bytes Data cache : 4K bytes • Internal RAM Instruction RAM : 4K ...
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INTERRUPT/EXCEPTION PROCESSING FUNCTION The features of the interrupt/exception processing function are as follows: • Interrupt • Non-maskable interrupt : 1 source • Maskable interrupt : 15 sources • Priority of the programmable interrupt can be specified in four levels ...
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Table 4-2. Maskable Interrupt List In- Classifi- Type cation Group Group Name Priority Mask- Interrupt GR3 3 RESERVED Reserved able 2 INTOV1 1 INTSER 0 INTP03 GR2 3 INTSR 2 INTST 1 INTCSI 0 INTP02 GR1 3 INTDMA 2 INTP10/ ...
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... BUS CONTROL FUNCTION The features of the bus control function are as follows: • Directly connects to EDO DRAM, Page-ROM, SRAM (ROM), or I/O • CAS access with 1 bus clock minimum • DRAM byte access control with four CAS signals • Wait control by READY signal • ...
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... DRAM. Addresses are output to the DRAM from the address pins by multiplexing row and column addresses. The connected DRAM must bits or more and have a hyper page mode (EDO). The refresh mode is a CAS-before-RAS (CBR) mode, and the refresh cycle can be arbitrarily set. ...
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... Table 7-1. Address Compared by on-page/off-page Decision Address Shift (3) Refresh function The BCU can automatically generate the distributed CBR refresh cycle necessary for refreshing the external DRAM. Whether refreshing is enabled or disabled and the refresh interval are set by the refresh control register (RFC). The BCU has a refresh request queue that can store refresh requests up to seven times. ...
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DMA FUNCTION The features of the DMA function are as follows: • Four independent DMA channels • Transfer unit: Bytes, half words (2 bytes), words (4 bytes) • Maximum number of transfers: 16,777,216 (2 • Transfer type: 2-cycle transfer ...
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The configuration of the DMA controller (DMAC) is shown below. Figure 8-1. DMAC Block Diagram Internal I/O ROM RAM I/O I/O DMAC Bus interface BCU DMA source address register (DSA) Address control block DMA destination address register (DDA) Counter control ...
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SERIAL INTERFACE FUNCTION The following channels are provided for the serial interface function. • Asynchronous serial interface (UART channel • Clocked serial interface (CSI) • Baud rate generator (BRG) 9.1 Asynchronous Serial Interface (UART) The features of ...
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The configuration of the asynchronous serial interface (UART) is shown below. Figure 9-1. Block Diagram of UART 16/8 RXB0 Receive buffer RXB0L Receive shift RXD Status register register TXD Receive control parity check 1/16 Remark = bus clock (33 M ...
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Clocked Serial Interface (CSI) The features of the clocked serial interface (CSI) are as follows: • High-speed transfer: 8.25 Mbps MAX. (bus clock: 33 MHz) • Half duplex communication for transmission/reception (buffer is not provided) • Character length: 8 ...
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Baud Rate Generator (BRG) 9.3.1 Configuration and function The serial interface can use the serial clock output by the baud rate generator or the divided value of (bus clock baud rate. The serial clock source is specified ...
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TIMER/COUNTER FUNCTION The features of the timer/counter function are as follows: • Measures pulse interval and frequency and outputs programmable pulse • 16-bit measurement • Can generate pulses of various shapes (interval pulse, one-shot pulse) • Timer 1 • ...
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The configurations of timer 1 and timer 4 are shown below. Figure 10-1. Block Configuration of Timer 1 Edge TCLR1 detection Note 1 m/4 /4 m/16 Note 2 TI Edge detection INTP10 Edge detection INTP11 Edge detection ...
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Figure 10-2. Block Configuration of Timer m/16 /8 m/32 Note Internal count clock Remarks 1. = bus clock ( 16.7 MHz intermediate clock 24 Note TM4 (16 bits) CM4 PD705101 Clear & ...
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PORT FUNCTION The features of the port function are as follows: • 3-bit input/output port which can be specified in 1-bit units • In addition to the port function, the port can operate as the I/O of the serial ...
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Figure 11-2. Block Diagram of Port 1 Control mode register (PC) Mode register (PM) Port register (PORT) Figure 11-3. Block Diagram of Port 2 Control mode register (PC) Mode register (PM) Port register (PORT PD705101 PORT1 PORT2 ...
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CLOCK GENERATION FUNCTION The features of the clock generation function are as follows: • Generation and control of CPU clock and bus clock supplied to each hardware unit • Bus clock ( ) : 16.7-33 MHz (f B • ...
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STANDBY FUNCTION The following two standby modes can be used. (1) HALT mode In this mode, the clock generator (oscillation circuit and PLL synthesizer) operates, but the operating clock of the CPU is stopped. The other internal peripheral functions ...
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Table 13-2. Operating Status in HALT/STOP Mode Function Oscillation circuit Operates PLL synthesizer Operates Bus clock Operates CPU Stops Port output Retained Peripheral function Operates Internal data Internal data such as registers of CPU retain status before HALT mode is ...
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RESET/NMI CONTROL FUNCTION The features of the reset/NMI control function are as follows: • RESET and NMI pins have noise rejection circuit that samples clock. • Performs forced reset, reset mask, and NMI mask processing from debug control unit ...
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INSTRUCTIONS 15.1 Instruction Format The V831 uses two instruction formats: 16-bit and 32-bit. The 16-bit instructions include binary operation, control, and conditional branch instructions, while the 32-bit instructions include load/store and I/O operation instructions, instructions for handling 16 bits ...
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Medium-distance jump instruction format [FORMAT IV] This instruction format has a six-bit operation code field and a 26-bit displacement field (the lowest-order bit must be 0), giving a total length of 32 bits opcode (5) Three-operand ...
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Instructions (Listed Alphabetically) The instructions are listed below in alphabetic order of their mnemonics. Explanation of list format Operand(s) Format CY OV Instruction ADD reg1, reg2 Instruction Instruction mnemonic format (See Section 15.1.) Abbreviations of operands Abbreviation reg1 General-purpose ...
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Instruction Operand(s) Format ABC disp9 III ABE disp9 III ABGE disp9 III ABGT disp9 III ABH disp9 III ABL disp9 III ABLE disp9 III ABLT disp9 III ABN disp9 III ABNC disp9 III ABNE disp9 III ABNH disp9 III ABNL ...
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Instruction Operand(s) Format CY AND reg1, reg2 I – ANDI imm16, V – reg1, reg2 BC disp9 III – BDLD [reg1], [reg2] VII – BDST [reg2], [reg1] VII – BE disp9 III – BGE disp9 III – BGT disp9 III ...
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Instruction Operand(s) Format CMP reg1, reg2 I imm5, rag2 DIV reg1, reg2 I DIVU reg1, reg2 HALT IX IN.B disp16[reg1], VI reg2 IN.H disp16[reg1], VI reg2 IN.W disp16[reg1], VI reg2 ...
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Instruction Operand(s) Format CY JAL disp26 IV – JMP [reg1] I – JR disp26 IV – LD.B disp16[reg1], VI – reg2 LD.H disp16[reg1], VI – reg2 LD.W disp16[reg1], VI – reg2 LDSR reg2, regID II MAC3 reg1, reg2, VIII – ...
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Instruction Operand(s) Format MACI imm16, V reg1, reg2 MACT3 reg1, reg2, VIII reg3 MAX3 reg1, reg2, VIII reg3 MIN3 reg1, reg2, VIII reg3 MOV reg1, reg2, I imm5, reg2 II MOVEA imm16, V reg1, reg2 MOVHI imm16, V reg1, reg2 ...
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Instruction Operand(s) Format CY MULI imm16, V – reg1, reg2 MULT3 reg1, reg2, VIII – reg3 MULU reg1, reg2 I – NOP III – NOT reg1, reg2 I – OR reg1, reg2 I – ORI imm16, V – reg1, reg2 ...
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Instruction Operand(s) Format SAR reg1 ,reg2 I imm5, reg2 II SATADD3 reg1, reg2, VIII reg3 SATSUB3 reg1, reg2, VIII reg3 SETF imm5, reg2 II SHL reg1, reg2 I imm5, reg2 II SHLD3 reg1, reg2, VIII reg3 ...
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Instruction Operand(s) Format CY SHR reg1, reg2 I imm5, reg2 II SHRD3 reg1, reg2, VIII – reg3 ST.B reg2, VI – disp16[reg1] ST.H reg2, VI – disp16[reg1] ST.W reg2, VI – disp16[reg1] STBY IX – STSR regID,reg2 II – SUB ...
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Instruction Operand(s) Format XOR reg1,reg2 I XORI imm16, V reg1,reg2 – 0 Exclusive OR. The exclusive OR of reg2 and reg1 is taken and written into reg2. – 0 Exclusive OR. The exclusive OR of ...
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... Storage temperature T stg Cautions 1. Do not connect an output (or input/output) pin device directly to any other output (or input/output) pin of the same device. Do not connect the V to its GND pin or a ground. Note, however, that these restrictions do not apply to the high- impedance pins of an external circuit, whose timing has been specifically designed to avoid output collision ...
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CAPACITANCE (T = –40 to +85˚ Parameter Symbol Input capacitance C I I/O capacitance C IO Remark These parameters are sample values, not the value actually measured. AC CHARACTERISTICS (T = –40 to +85˚ test ...
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Clock input (X2) timing (when external clock used) Parameter Symbol External clock cycle <1> t CYX External clock high-level time <2> t XXH External clock low-level time <3> t XXL External clock rise time <4> External clock ...
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... Notes 1. At power application or when returned from STOP mode, and the internal clock is generated power application or when returned from STOP mode, and the internal clock is generated, after clock has stabilized. 3. When clock has stabilized under conditions other than Notes 1 and 2. Remark It is not necessary to satisfy t the reset acknowledge timing may be shifted. 0 ...
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DRAM access timing Parameter BCYST delay time (vs. CLKOUT ) Address delay time (vs. CLKOUT ) RAS delay time (vs. CLKOUT ) CAS delay time (vs. CLKOUT ) CAS signal interval CAS high-level time CAS low-level time CAS rise ...
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CBR refresh, CBR self refresh timing CLKOUT (output) <17> RAS (output) xxCAS (output) REFRQ (output) 48 <17> <18> <26> PD705101 <17> <18> <26> ...
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DRAM single 1-clock CAS off-page cycle (32-bit data bus) Trm CLKOUT (output) BCYST (output) <16> A1-A23 (output) <17> RAS (output) xxCAS (output) <24> WE (output) <25> OE (output) D0-D31 (input) D0-D31 (output) Remark The dotted lines indicate high impedance. ...
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DRAM single 1-clock CAS on-page cycle (32-bit data bus) CLKOUT (output) <15> BCYST (output) <16> A1-A23 (output) RAS (output) xxCAS (output) <24> WE (output) <25> OE (output) D0-D31 (input) <29> D0-D31 (output) <30> D0-D31 (output) Remark The dotted lines ...
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DRAM single 2-clock CAS off-page cycle (32-bit data bus) Trm CLKOUT (output) BCYST (output) <16> <16> A1-A23 (output) <17> RAS (output) xxCAS (output) <24> WE (output) <25> OE (output) D0-D31 (input) D0-D31 (output) Remark The dotted lines indicate high ...
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DRAM single 2-clock CAS on-page cycle (32-bit data bus) CLKOUT (output) <15> BCYST (output) <16> A1-A23 (output) RAS (output) xxCAS (output) <24> WE (output) <25> OE (output) D0-D31 (input) <29> D0-D31 (output) <30> D0-D31 (output) Remark The dotted lines ...
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DRAM burst 1-clock CAS off-page cycle (32-bit data bus) Trm Trp CLKOUT (output) BCYST (output) <16> <16> A1-A23 (output) <17> RAS (output) xxCAS (output) <24> WE (output) <25> OE (output) D0-D31 (input) D0-D31 (output) Remark The dotted lines indicate ...
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DRAM burst 2-clock CAS off-page cycle (32-bit data bus) Trm Trp Trc CLKOUT (output) BCYST (output) <16> <16> RA A1-A23 (output) <17> <17> RAS (output) xxCAS (output) <24> WE (output) <25> OE (output) D0-D31 (input) D0-D31 (output) Remark The ...
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SRAM (ROM), Page-ROM, I/O access timing Parameter BCYST delay time (vs. CLKOUT ) Address delay time (vs. CLKOUT ) Data output delay time (from active, vs. CLKOUT ) <29> t Data output delay time (from float, vs. CLKOUT ) ...
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I/O access timing CLKOUT (output) BCYST (output) A1-A23 (output) CS (output) IORD (output) D0-D31 (input) IOWR (output) D0-D31 (output) D0-D31 (output) READY (input) Remark The dotted lines indicate high impedance <15> <15> <16> <32> <33> ...
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SRAM (ROM)/Page-ROM single cycle CLKOUT (output) <15> BCYST (output) <16> A1-A23 (output) <32> CS (output) MRD (output) D0-D31 (input) xxMWR (output) <29> D0-D31 (output) <30> D0-D31 (output) READY (input) Remark The dotted lines indicate high impedance ...
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Page-ROM burst cycle (32-bit data bus) Ta Tb1 CLKOUT (output) <15> <15> BCYST (output) <16> A1-A23 (output) <32> CS1-CS7 (output) <33> MRD (output) D0-D31 (input) <39> <40> <39> <40> READY (input) Remark The dotted lines indicate high impedance. 58 ...
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Interrupt timing Parameter NMI setup time (vs. CLKOUT ) NMI hold time (vs. CLKOUT ) INTPxx setup time (vs. CLKOUT ) INTPxx hold time (vs. CLKOUT ) NMI clock high-level time NMI clock low-level time Remark ...
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Bus hold timing Parameter Data active delay time (vs. CLKOUT ) Data float delay time (vs. CLKOUT ) HLDRQ input setup time (vs. CLKOUT ) HLDRQ hold time (vs. CLKOUT ) HLDAK output delay time Address float delay time ...
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DMA timing Parameter DMARQ input setup time (vs. CLKOUT ) DMARQ hold time (vs. CLKOUT ) DMAAK output delay time CLKOUT (output) <52> DMARQ0-DMARQ3 (input) DMAAK0-DMAAK3 (output) Symbol Conditions <52> t SDQK <53> t HKDQ <54> t DKDAK <53><52> ...
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CSI timing (a) SCLK input mode Parameter SCLK cycle SCLK high-level time SCLK low-level time SCLK rise time SCLK fall time SI input setup time (vs. SCLK ) SI input hold time (vs. SCLK ) SO output delay time ...
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SCLK output mode Parameter SCLK cycle SCLK high-level time SCLK low-level time SCLK rise time SCLK fall time SI input setup time (vs. SCLK ) SI input hold time (vs. SCLK ) SO output delay time (vs. SCLK ) ...
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Timer timing Parameter TI clock cycle TI clock high-level time TI clock low-level time TI clock rise time TI clock fall time TCLR clock high-level time TCLR clock low-level time Remark (external clock cycle) CYK 2.0 ...
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PACKAGE DRAWINGS 160 PIN PLASTIC LQFP (FINE PITCH) ( 24) 120 121 160 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. A ...
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RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the PD705101. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case ...
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PD705101 67 ...
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PD705101 ...
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... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • ...
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... Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...