PXB4220EV3.4 Infineon Technologies AG, PXB4220EV3.4 Datasheet
PXB4220EV3.4
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PXB4220EV3.4 Summary of contents
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... Edition 2001-07 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 7/27/01. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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PXB4219E/PXB4220E/PXB4221E PRELIMINARY Revision History: Previous Version: Page Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.2.1.2 HEC Check: Header Error Detection and Correction . . . . . . . . . . . . 51 4.2.1.3 Cell Payload Descrambling . . . . . . . . . . . . ...
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Table of Contents 4.5.10 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 5.4 Clock Recovery Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 7.5 OAM-Counter Enable Register for AAL Ports (caal 159 7.6 Byte-Pattern Register bp3 and bp2 (bp32 ...
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Table of Contents 7.47 Configuration Register Downstream of Port N (condN 205 7.48 Interrupt Source of Port N (irsN ...
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Table of Contents 9.6.1 Clock and Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 40 ACM Jitter Tolerance in E1 Mode with Jitter Attenuator . . . . . . . . . . 232 Figure 41 ACM Jitter Tolerance in T1 Mode without Jitter Attenuator . . . . ...
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List of Tables Table 1 Generic Framer Interface (73 pins Table 2 ...
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List of Tables Table 42 Transmit Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Single PHY) . 259 Table 43 Receive Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Single PHY). . 259 Table 44 Transmit Timing (8-Bit ...
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PRELIMINARY Your Comments We welcome your comments on this document. We are continuously trying improving our documentation. Please send your remarks and suggestions by e-mail to com.docu_comments@infineon.com Please provide in the subject of your e-mail: device name (IWE8), device number ...
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PRELIMINARY 1 Overview The Interworking Element for 8 E1/T1 Lines PXB4219E/PXB4220E/PXB4221E (IWE8 member of Infineon’s ATM chip set. Together with framing and line interface components (e.g. Infineon’s QuadFALC PEB 22554) the IWE8 serves as gateway between Asynchronous Transfer ...
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PRELIMINARY Interworking Element for 8 E1/T1 Lines IWE8 Version 3.4 1.1 Features • Full duplex ATM Packetizer/Depacketizer for 8 E1/T1 highways • Configurable mode via external pin • 8 T1/E1 ports configurable independently to ATM or ...
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PRELIMINARY – Internal clock recovery circuit using Synchronous Residual Time Stamp (SRTS, for fully filled cells only) or Adaptive Clock Method (ACM) for unstructured CES ports. For SRTS a patent fee needs to be paid. Optionally, it’s possible to order ...
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PRELIMINARY 1.2 Logic Symbol CR Interface MPDATA[0:15] MPADR[0:17] Micro- MPCS processor MPWR Interface MPRD MPRDY MPIR1,2 RMADR[0:15] RMDAT[0:32] RMCS RAM RMOE Interface RMWR RMCLK RMADC Figure 1 Logic Symbol Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E Test Interface PXB ...
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PRELIMINARY 1.3 Typical Applications Figure 2 illustrates three typical application areas which utilize the IWE8 chip in Line Interface Cards (LICs) or Network Interface Controllers (NICs). Application 1 utilizes the IWE8 as an internetworking device for communication between a narrowband ...
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PRELIMINARY 1.3.1 Line Card Figure 3 shows an example Line Interface Card (LIC) utilizing the IWE8 in a switch environment. Two Infineon Quad Framer and Line Interface Component (QuadFALC, PEB 22554) chips are connected at the PCM ports. An ATM ...
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PRELIMINARY PDH FALC LH PEB2255 network Near End Figure 4 Echo Canceller Application The echo cancelling function itself is performed in STM. In the application above the IWE8 is used to translate voice ATM channels into STM channels and vice ...
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PRELIMINARY 1.4 Differences Between PXB4220 And PXB4219 The IWE8 type PXB4219 does only support the ATM mode used for ITU-T G.804 compliant ATM cell mapping into the plesiochronous digital hierarchy (PDH) at line rates of 1544 kbit/s and 2048 kbit/s. ...
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PRELIMINARY 2 Pin Descriptions 2.1 Pin Diagram FTCKO MPDAT 1 GND TCK TMS MPWR _4 FTMFS FTDAT FTCKO MPDAT 2 TDO MPCS FRMFB FRFRS FTFRS 3 N.C. TRST MPRD ...
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PRELIMINARY 2.2 Pin Definitions and Functions Output Pull Up and Pull Down Type Definitions PUx PDx Tri 2.2.1 Generic Framer Interface Table 1 Generic Framer Interface (73 pins) Pin No. Symbol C5, A6, B9, FRCLK[7:0] A12, C14, A18, C19, G17 ...
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PRELIMINARY Table 1 Generic Framer Interface (73 pins) (cont’d) Pin No. Symbol C4, D5, C2, FTCKO[7:0] B1, C13, B16, A20, D20 B2, D7, B8, FTDAT[7:0] B10, A13, C15, B18, D19 A2, C6, C8, FTMFS[7:0] C10, D12, D14, B17, C20 C3, ...
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PRELIMINARY 2.2.2 UTOPIA Interface Table 2 UTOPIA Interface (36 pins) Pin No. Symbol U12, V12, RXDAT[7:0] W12, Y12, U11, V11, W11, Y11 Y13 RXPTY W10 RXSOC V10 RXCLAV V13 RXCLK W13 RXENB Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E ...
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PRELIMINARY Table 2 UTOPIA Interface (36 pins) (cont’d) Pin No. Symbol V5, Y4, Y3, RXADR[4:0] U5, V4 U9, Y8, TXDAT[7:0] W8, V8, Y7, W7, V7 TXPTY W6 TXSOC V6 TXCLAV Y9 TXCLK Preliminary Data Sheet PXB4219E / PXB4220E ...
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PRELIMINARY Table 2 UTOPIA Interface (36 pins) (cont’d) Pin No. Symbol U7 TXENB W4, Y2, TXADR[4:0] W3, Y1, W2 2.2.3 IMA Interface Table 3 IMA Interface Pin No. Symbol Y10 ATBTC L20 UNCHEC Y5, W5, PN[2:0] M1 Preliminary Data Sheet ...
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PRELIMINARY 2.2.4 Clock Recovery Interface Table 4 Clock Recovery Interface Pin No. Symbol Y18 SDI Y20 SDOD W20 SDOR T17 SSP T20 SCLK 2.2.5 Microprocessor Interface Table 5 Microprocessor Interface Pin No. Symbol K1, K3, K2, MPDAT[15:0] J1, J2, J3, ...
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PRELIMINARY Table 5 Microprocessor Interface (cont’d) Pin No. Symbol E1 MPWR/ MPRW F3 MPRD/ MPTS L4 MPRDY MPTA M2 MPIR1 M3 MPIR2 Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E Input (I) Function Output (O) I Microprocessor Write Enable (Intel ...
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PRELIMINARY 2.2.6 External RAM Interface Table 6 External RAM Interface Pin No. Symbol F19, G18, RMADR[15:0] F20, G19, G20, H18, H19, H20, J17, J18, J19, J20, K17, K18, K19, K20 M18, M17, RMDAT[32:0] N20, N19, N18, P20, P19, P18, R20, ...
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PRELIMINARY Table 6 External RAM Interface (cont’d) Pin No. Symbol L18 RMADC W14 RMCLK 2.2.7 Test Interface Table 7 Test Interface Pin No. Symbol D2 TDO E4 TDI C1 TCK D1 TMS E3 TRST V3 TSCEN A11 TSCSH Y15 PMT ...
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PRELIMINARY Table 7 Test Interface (cont’d) Pin No. Symbol W9 UTTR Y14 OUTTR 2.2.8 Miscellaneous Table 8 Miscellaneous Pin No. Symbol W1 E1/ CLOCK L3 RESET V2 CLK52 Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E Input ...
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PRELIMINARY 2.2.9 Power Supply Table 9 Power Supply Pin No. Symbol D6, D11, VDD D15, F4, F17, K4, L17, R4, R17, U6, U10, U15 A1, D4, D8, GND D13, D17, H4, H17, N4, N17, U4, U8, U13,U17 2.2.10 Not Connected ...
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PRELIMINARY 3 Functional Description All functional parts of the device are implemented in hardware. Configuration of the functional blocks has to be done by software via the micro controller interface. The IWE8 provides two independent data paths for upstream, towards ...
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PRELIMINARY 3.1 Operating Modes 3.1.1 ATM Mode A port that is configured to ATM mode offers ITU-T G.804 [26] compliant ATM cell mapping into PDH frames datarates. ATM mode can be enabled via “p_atm” in register ...
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PRELIMINARY 3.1.2.2 Structured CES Mode A port is programmed for the Structured T1/E1 Nx64 kbit/s Basic Service (Structured CES) via the port configuration register “pcfN” (“p_ces” = 0). The structured circuit emulation service is intended to carry N of the ...
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PRELIMINARY 3.2 Functional Block Diagram CV ICRC External Clock Recovery Recovery Interface Framer Receive Interface Processing SL x8 Serial Loop Framer Transmit Interface Processing CK EQ Clock & Reset Figure 6 Block Diagram Preliminary ...
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PRELIMINARY 3.3 Functional Block Description Table 11 Functions of IWE8 Blocks Block Functions FR Framer Receive interfaces • FRCLK synchronization • 8 bit serial to parallel conversion • Frame and multiframe synchronization • Timeslot counter • Timeslot assignment and channel ...
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PRELIMINARY Table 11 Functions of IWE8 Blocks Block Functions UL Upstream Loop • Cell loopback from Cell Receive to Cell Transmit processing • Loopback buffer for 4 cells DL Downstream Loop • Cell loopback from UTOPIA Transmit to UTOPIA Receive ...
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PRELIMINARY Table 11 Functions of IWE8 Blocks Block Functions OT Octet Transmit processing ATM ports: • Reading octets from ATM Transmit Buffer • Cell rate de coupling: idle/unassigned cell insertion • Cell payload scrambling • HEC generation AAL ports: • ...
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PRELIMINARY Table 11 Functions of IWE8 Blocks Block Functions CV External Clock Recovery interface • Generation of serial communication frames to external clock recovery circuit, containing RTS values and or ACM buffer filling • Generation of synchronization for RTS generation ...
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PRELIMINARY 4 Operational Description 4.1 ATM Transmit Functions For ports configured to ATM mode the following data flow is valid: The Cell Transmit Processing block is responsible for: • Cell discarding • Write ATM cells except of UDF octet to ...
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PRELIMINARY pressure state. This results in two side effects, which have to be taken into account for the calculation of threshold values. • After back pressure state has been entered additional cells may be transferred from the ...
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PRELIMINARY octet 1 GFC[3:0]/VPI[11:8] = prg_tx_hd[7:4] octet 2 VPI[3:0] = 0000 octet 3 octet 4 VCI[3:0] = 0000 octet 5 octet 6 . octet 53 • If idle cell insertion according to ITU-T I.361 or ITU-T I.432.1 is desired, the ...
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PRELIMINARY • the receiver must subtract (equal to add modulo 2) the same pattern from the 8 HEC bits before calculating the syndrome of the header example, if the first 4 octets of the header were all zeros ...
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PRELIMINARY 4.2 ATM Receive Functions For ports configured to ATM mode the following data flow is valid: The Octet Receive Processing block is responsible for: • Cell delineation • HEC check: Header error detection and correction • Cell payload de-scrambling ...
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PRELIMINARY • for the Cell-based Physical Layer, ALPHA = 7 and DELTA = 8. • for the Frame-based Physical Layer, ALPHA = 7 and DELTA = 6. • for other systems, values for ALPHA and DELTA are for further study. ...
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PRELIMINARY The Loss of Cell Delineation (LCD) state is entered whenever the Out of Cell (OCD) state is continuously active for more than an user defined period of time, ITU-T I.432.1 recommends a persistence time of 50ms. For each port ...
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PRELIMINARY . No error detected Figure 10 HEC Detection According to ATM Forum No discarding of HEC errored cells as an option is available and selectable via bit “a_hec_mode” in the register acfg indicated by setting the most significant bit ...
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PRELIMINARY Idle cell identification (Notes 1 and 2) Physical OAM cell identification (Note 2) layer Reserved for use of the physical layer (Notes 1, 2 and 3) P: Indicates the bit is available for use by the physical layer Values ...
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PRELIMINARY If all physical layer cells should be deleted, the “msk_rx_hd” should be set to 1111 1110. • For ATM Forum compliance, the “prg_rx_hd” field should be set to 0000 0000. The “msk_rx_hd” should be set to 1111 1110. This ...
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PRELIMINARY 4.3 AAL Segmentation Functions This function implements the Convergency Sublayer for Structured Data Transfer (SDT) and Unstructured Data Transfer as well as the Segmentation Sublayer for AAL type 1 as described in ITU-T recommendation I.363.1 [31]. The structure of ...
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PRELIMINARY In SDT mode, the cells are segmented when the first (multi) frame synchronization pulse after segmentation start is received from the framer receive interface of that channel. The resulting SC value and pointer field of the first cell transmitted ...
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PRELIMINARY 4.3.1.4 Transport of CAS Information The four CAS bits for each timeslot are transported within one multiframe from the framer to the IWE8. A signalling buffer in the internal RAM (256 2bit) holds the CAS bits ...
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PRELIMINARY 4.3.1.6 Segmentation Buffer The Segmentation Buffer is located in external RAM providing 256 bytes of memory for each timeslot, totalling for 8 ports with 32 timeslots each. The buffer for each timeslot consists of 4 blocks ...
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PRELIMINARY Table 17 Cell Filling level values ATM Adaptation Layer Type Minimum AAL0 4 AAL1 4 AAL1 with CAS 4+ frame based SDT without CAS is used and filling level fulfilled for correct operation. Multiframe based SDT without ...
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PRELIMINARY The RTS value stored in the RTS buffer of the port is loaded from the Internal Clock Recovery Circuit ICRC or from the Clock Recovery Interface. A new value will be provided by the ICRC once every cycle of ...
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PRELIMINARY 4.4 AAL Reassembly Functions When AAL type 0 is enabled in the “AAL Transmit Reference Slot”, the SAR-PDU and SAR-SDU processing is disabled. When AAL type 0 is disabled in the “AAL Transmit Reference Slot”, the SAR-PDU header is ...
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PRELIMINARY 4.4.1.3 Sequence Number field check This function implements the sequence number processing. It can be enabled via bit “sn_check” in the “AAL Transmit Reference Slot”. If enabled, selection can be made between Robust and Fast Sequence Count Algorithm as ...
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PRELIMINARY The bit “sdt_par” in the “AAL Transmit Reference Slot” allows to disable the verification of the parity bit in the pointer field. For multiframe based SDT the bit “sdt_mfs” in the “AAL Transmit Reference Slot” has to be set. ...
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PRELIMINARY The number of memory blocks used depends on the bandwidth of the channel (N*64- kbit/s). Thus for structured CES with N*64-kbit/s there are memory blocks per connection. The one-to-one relationship between timeslots and groups of memory ...
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PRELIMINARY The action chosen is determined by the “auto_reinit_uf” field in the “AAL Transmit Reference Slot” in RAM3. For AAL type 0 the detection of an underflow period is considered to be the detection of cell loss. For this reason ...
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PRELIMINARY • In “Inactive” mode, no cells are accepted from the “UTOPIA Transmit interface”, and byte-pattern 0 is sent to the framer transmit interface. • In “Standby” mode, cells are accepted from the “UTOPIA Transmit interface”, but byte- pattern 0 ...
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PRELIMINARY 4.4.2.3 Initialization of the Reassembly Buffer Before a channel is activated, the Reassembly Buffer must be configured properly to compensate Cell Delay Variation (CDV). In order to avoid buffer underflow due to large cell distances the amount of initial ...
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PRELIMINARY As the transmission of the reassembled cell stream is delayed by “starv_ini”+1 octets, there will be “starv_ini”+1 octets of the previous cell left in the Reassembly Buffer if the following cell arrives without CDV. If the maximum positive CDV ...
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PRELIMINARY Reassembly Buffer Filling Level [octets] buff_lsize 4 0 Framer T T +CDV Interf. T +CDV 0 Starvation octets Data octets Figure 17 Reassembly Buffer Initialization: Negative CDV at Start Up If the first cell has maximum negative ...
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PRELIMINARY Transmit Interface requests the first time-slot octet belonging to the channel in the frame or the multiframe. From that moment on, the “ATM Start of Structure” and “Port Start of Structure” are synchronous and the contents of the Reassembly ...
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PRELIMINARY with maximum negative CDV. the following cell arrives with maximum negative CDV. In case the following cell arrives with maximum positive CDV it will be “starv_ini” plus the amount of data to be transmitted in the expectation ...
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PRELIMINARY 4.4.2.4 Re-Initialization of the Reassembly Buffer For re-initialization of the Reassembly Buffer by the microprocessor, the processor has to set the “mcp_reinit” bit in the “AAL Transmit Reference Slot” in RAM2, wait for 1.5 frames and reset “mcp_reinit”. Preliminary ...
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PRELIMINARY 4.5 Internal Clock Recovery Circuit (ICRC) The Internal Clock Recovery Circuit (ICRC) may generate RTS values in upstream direction and a 8.192, 2.048 or 1.544 MHz transmit clock in downstream direction. Each port works independently using its own set ...
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PRELIMINARY Receive Line RTS 0 Clock generation 1 lgc 2.43 MHz 32.768 MHz Loopback 1 PLL Transmit 1 SRTS Line PLL 0 Clock FILTER PLL lc8 ACM PLL Microprocessor Interface, Test and Control Figure 19 Block Diagram of the ICRC ...
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PRELIMINARY The frame receiver is synchronized to the received synchronization signal PDSYN by means of an internal synchronization counter. In case no sync signal is received, frames are synchronized to the counter. The synchronization between PDSYN and the internal counter ...
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PRELIMINARY case bit “ena” of register “tsinN” is set, a value from the SRTS Receive FIFO is read by reading register “tsout”. In cases where the network clocks of RTS generator and RTS receiver have a frequency offset, the SRTS ...
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PRELIMINARY work properly with these RTS values via bit “pwd” of “condN”. If “srt” in “condN” is reset, the output of the RTS Receive FIFO is not used by PLL-SRTS. 4.5.8 Fractional Divider The fractional divider generates a 2.43 MHz ...
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PRELIMINARY 4.5.11.2 PLL-FILTER The PLL “PLL-FILTER” has a very low cut off frequency and a tuning range of ±240 ppm. It reduces jitter which is generated in, or passed through PLL-SRTS. Although PLL- FILTER is placed behind PLL-ACM, it has ...
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PRELIMINARY The tuning range of the DCO is limited to the value programmed to bits “tur” in register “condN”. If the phase detector requests a higher frequency deviation the DCO enters out-of-range condition. In this case the DCO’s output will ...
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PRELIMINARY During start-up and restart, PLL-ACM will be free running for 8 x tiniN[tini programmed in the Time of Initial Free Run Register (“tiniN”, see this time the data buffer is filled with an initial number of bytes. ...
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PRELIMINARY 4.6 Internal Queues 4.6.1 Event Queue All the functional blocks that process octets or cells can generate counter events, i.e. commands to increment a particular counter in the external RAM. All counter events are written in a FIFO queue ...
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PRELIMINARY 4.7 OAM Processing The OAM processing block (OM) will read Statistics Counter events from the Event Queue as long as the Event Queue is not empty. The OM will read the Statistics Counter value “count_value” and the Statistics Counter ...
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PRELIMINARY 4.8 Loopback Modes 4.8.1 Upstream Loop The Upstream Loop block (UL) allows cells that are received at the Framer Interface and forwarded to the UTOPIA Receive Interface to be send back via the UTOPIA Transmit Interface to the Transmitter ...
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PRELIMINARY 4.8.3 Serial Loop The framer transmit clock, data, framesync and multi-framesync signals can be looped from the Framer Transmit Interface to the Framer Receive Interface per port. This feature can be enabled by setting the “p_slp” bit in the ...
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PRELIMINARY 4.9 Cell Insertion This block allows the insertion of predefined cells stored in the Cell Insertion Buffer into the UTOPIA receive cell stream. The Cell Insertion Buffer, located in external RAM, offers space for one ATM cell. The ATM ...
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PRELIMINARY 4.10 Cell Extraction Cells coming in downstream direction from the UTOPIA Transmit Interface can be extracted to the Cell Extraction Buffer instead of the Reassembly/ATM Transmit Buffer. The Cell Extraction Buffer offers space for 254 ATM cells ...
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PRELIMINARY 4.11 Mapping of Channels to Timeslots The two LSB bits of a slot entry identify the slot type: Table 21 Coding of Slot Type in internal configuration RAMs Slot Type ATM/AAL Idle ATM/AAL Continuation ATM/AAL Reference 4.11.1 ATM Mode ...
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PRELIMINARY Table 22 RAM slot positions for ITU-T G.804 compliant ATM mapping RAM E1 Slot Slot RAM Slot Type 10 10 ATM Continuation 11 11 ATM Continuation 12 12 ATM Continuation 13 13 ATM Continuation 14 14 ATM Continuation 15 ...
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PRELIMINARY programmed with one Reference Slot at RAM slot 0. This slot number is used to identify the channel (“channel_nr” = 0). 4.11.2.2 Structured CES For AAL ports with structured CES (Nx64 kbit/s) service, the timeslots are grouped into channels ...
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PRELIMINARY Table 23 AAL Idle slot positions for structured CES in AAL mode Slot number E1 13 AAL Ref./Cont./Idle 14 AAL Ref./Cont./Idle 15 AAL Ref./Cont./Idle 16 AAL Idle 17 AAL Ref./Cont./Idle 18 AAL Ref./Cont./Idle 19 AAL Ref./Cont./Idle 20 AAL Ref./Cont./Idle ...
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PRELIMINARY In T1 mode in GIM things are different. RAM slot 0 may also be used for user data, with “channel_mode” and “band_width” set according to the requirements of the user data carried via that slot. Table 24 AAL Idle ...
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PRELIMINARY Table 24 AAL Idle slot positions for structured CES with CAS in AAL mode Slot number E1 23 AAL Ref./Cont./Idle 24 AAL Ref./Cont./Idle 25 AAL Ref./Cont./Idle 26 AAL Ref./Cont./Idle 27 AAL Ref./Cont./Idle 28 AAL Ref./Cont./Idle 29 AAL Ref./Cont./Idle 30 ...
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PRELIMINARY 5 Interface Description 5.1 Generic Framer Interface The selection of the Echo Canceller mode is done via an external pin (Pin EC = 0). In standard mode (Pin EC = 1), 4 sub modes can be selected via the ...
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PRELIMINARY The data is transferred between the FALC and the IWE8 via a system internal highway. FRCLK[7:0] Framer Receive Clock Receive system clock of 8.192 MHz (falling) FRDAT[7:0] Framer Receive Data FRDAT is sampled in the middle of the bit ...
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PRELIMINARY FTFRS[7:0] Framer Transmit Frame Synchronization Pulse FTFRS is generated at the beginning of timslot 1 of every frame RFCLK Reference Clock • Reference clock for the internal clock recovery circuit • Depending on p_rx_em in ...
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PRELIMINARY Framer Receive Interface: FRCLKn FRDATn 248 249 250 251 252 FRMFBn FRFRSn timeslot 31 Framer ...
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PRELIMINARY Table 25 Time slot Mapping in T1 Translation Mode 0 (cont’d) Frame slot T1 channel 10 channel 8 11 channel channel 10 14 channel 11 15 channel 12 The F-channel only contains the F-bit. Its location ...
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PRELIMINARY FRMFB[7:0] Framer Receive Multiframe Begin Depending on bits p_ces in pcfN: Depending on bit “rfpp” in “opmo”: FRMFB is always sampled with the falling edge of FRCLK. FRFRS[7:0] Framer Receive Frame Synchronization Pulse Permanently inactive FRLOS[7:0] Framer Receive Loss ...
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PRELIMINARY Depending on bit “tfpp” in “opmo” FTFRS[7:0] Framer Transmit Frame Synchronization Pulse FTFRS is asserted synchronously to the transmission of the F-bit of each frame. RFCLK Reference Clock • Reference clock for the internal clock ...
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PRELIMINARY 5.1.2.2 E1 Mode FRCLK[7:0] Framer Receive Clock Receive clock input with 2.048 MHz FRDAT[7:0] Framer Receive Data depending on bit “frri” in “opmo” FRMFB[7:0] Framer Receive Multiframe Begin Depending on bits p_ces in pcfN: depending ...
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PRELIMINARY Depending on bit p_ces in pcfN Depending on bit “tfpp” in “opmo” FTFRS[7:0] Framer Transmit Frame Synchronization Pulse FTFRS is asserted synchronously to the transmission of the first bit of the ...
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PRELIMINARY 5.1.3 Synchronous Modes (SYM) In these modes, transmit and receive channels are synchronized. Therefore, they may be used for synchronization of frame and multiframe based protocols, e.g. Frame based SDT on E1-Lines. Only one central clock, the external reference ...
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PRELIMINARY depending on bit “symn” in “opmo” FRMFB is always sampled with the opposite clock-edge of FRDAT. FRFRS[7:0] Framer Receive Frame Synchronization Pulse Unused FRLOS[7:0] Framer Receive Loss of Signalling FTCKO[7:0] Framer ...
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PRELIMINARY 5.1.3.2 Synchronous Mode at 8.192 MHz (SYM8) In SYM8 mode the framer interface is clocked with an 8.192 MHz clock connected to RFCLK. The mode is enabled by setting bit All timeslots (transmit and receive) will ...
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PRELIMINARY FTFRS[7:0] Framer Transmit Frame Synchronization Pulse Unused RFCLK Reference Clock Central framer interface clock with 8.192 MHz RFCLK FRDATn ...
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PRELIMINARY FTMFS[7:0] Framer Transmit Multiframe Synchronization Unused FTFRS[7:0] Framer Transmit Frame Synchronization Pulse FTFRS[0] is asserted synchronously to the transmission of the first bit of the first timeslot of each frame. FTFRS[1:7] are unused RFCLK Reference Clock Central framer interface ...
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PRELIMINARY 5.2 UTOPIA Interface Figure 29 UTOPIA Receive and Transmit Interfaces in Slave Mode The UTOPIA receive and transmit interfaces are implemented according to the ATM forum UTOPIA Level 2 Specification [6] and to the UTOPIA Level 1 Specification [5]. ...
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PRELIMINARY In case it is configured for UTOPIA level 2 MPHY mode, the amount of implemented PHY ports can be selected via the associated address range (“utconf[utrange]” with utconf[mapping_mode] = 0). In addition, the transmission of the UTOPIA port number ...
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PRELIMINARY 5.2.2.2 Port Specific Backpressure Mechanism In addition to the general backpressure mechanism, port specific backpressure is available for ATM ports, when using the IWE8 as a UTOPIA level 2 PHY device (“utconf[utlevel]” =0, “utmaster” “mapping_mode” =0 and ...
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PRELIMINARY MSB port_nr[2:0] GFC[3:1] / VPI[11:9] VPI[3:0] VCI[11:8] channel_nr[3:0] VCI[3:0] HEF CLPI ENB UDF[7] UDF[6] UDF[5] Figure 30 Utopia Sideband Signals Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E port_nr[2:0] GFC[0] VPI[7:5] / VPI[8] port_nr[2:0] VCI 15..13 port_nr[2:0] VCI[7:5] PTI ...
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PRELIMINARY 5.3 IMA Interface The IWE8 has provisions to support the Inverse Multiplexing over ATM (IMA) protocol implemented in an external component. These are: • An IMA interface • A programmable threshold between read and write pointer of the mapping ...
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PRELIMINARY 5.4 Clock Recovery Interface It is possible to use an external device for clock recovery instead of the ICRC. Therefore an external clock recovery interface is provided. It allows the transmission and reception of serial communication frames containing SRTS ...
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PRELIMINARY To allow the external SRTS generation logic to synchronize with the cell segmentation process, the IWE8 will output a frame with type = 111 on the SDOR signal when the segmentation of the first ATM cell for a selected ...
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PRELIMINARY 5.5 Microprocessor Interface IWE8 contains internal registers, 4 internal RAMs and an external RAM that can be read and written via the Microprocessor Interface. As access to the internal registers is 16-bit oriented, the Microprocessor Address Bus (MPADR) is ...
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PRELIMINARY 5.5.2 Microprocessor Interface Mode The IWE8 microprocessor interface allows connection of Intel type microprocessors as well as Motorola type microprocessors (e.g. the PowerPC). The Microprocessor Interface Mode is determined via the status of the pins PMT and TBUS at ...
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PRELIMINARY MC 68xxx DSACK1 CSn R/W DATA[0-15] A[1-18] Figure 33 Connection of IWE8 to an Motorola Type Microprocessor Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E INTi INTj DS 116 IWE8 V3.4 Interface Description IWE8 MPIR2 MPIR1 MPTA MPCS MPTS ...
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PRELIMINARY 5.6 External RAM Interface The IWE8 needs to be connected to an external synchronous SRAM of 64k x 33 bits with parity protection or 64k x 32 bits without parity protection. For proper operation FT (Flow Through) SSRAM is ...
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PRELIMINARY 5.7 Boundary Scan Interface The boundary scan interface implements the Test Access Port (TAP) as defined in IEEE Standard 1149.1-1990 [19] including the optional TRST reset signal. The device identification register, the instruction register and boundary-scan register are described ...
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PRELIMINARY 5.8 Master Clock The basic processing time of an octet in the IWE8 is 12 clock cycles. As the time needed to process one octet for each of the 8 ports must be less than the time required to ...
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PRELIMINARY 6 Memory Structure The IWE8 occupies an address space of 256k x 16 bits. The lower 128k x 16 bits are used for internal registers and internal configuration RAM’s. The upper 128k x 16 bits are used to address ...
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PRELIMINARY The external RAM is organized as a 64k x 32 bit parity protected memory. Accesses to internal configuration RAM’s or external RAM are always 32 bit oriented. 6.1 Internal Configuration RAM’s The 4 internal 256 x 32 bit configuration ...
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PRELIMINARY 6.1.1 RAM1: Receive Port Configuration Read/write Address 00200 Reset value: Not applicable. RAM must be reset and initialized via SW Memory size 256K 32 bits: 8 ports x 32 slots x 1 doubleword MPADR ...
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PRELIMINARY 0 = Cell delineation finite state machine normal operation 1 = Cell delineation finite state machine forced in hunt state Only the transition 0 of times SYNC state is left) is not incremented. Ocd_start interrupt is not generated. delete_idle_ ...
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PRELIMINARY Not used ref_slot_nr Reference slot number Number of the reference slot of this channel cont_slot Continuation slot indicator 1 = This slot is a continuation slot ref_slot Reference slot indicator 0 = This slot is ...
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PRELIMINARY next_slot_nr Next slot number If band_width > 0 next_slot_nr points to the next slot of this channel. If band_width = 0 and CAS is activated next_slot_nr[3:0] will be used as signalling conditioning nibbles. If band_width = 0 and CAS ...
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PRELIMINARY 4 to AAL0: 48 [aal0 AAL1 unstructured CES: 47 [aal0 pcfN[p_ces AAL1 structured CES without CAS 47 [aal0 pcfN[p_ces pcfN[p_cas 4+Cb AAL1 structured ...
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PRELIMINARY 6.1.1.4 RAM1: AAL Receive Continuation Slot Read/write Address 00200 Reset value: Not applicable. RAM must be reset and initialized via SW. 31 next_slot_nr[4:0] 23 Not used 15 fourth_slot_nr[3:0] 7 third_slot _nr[0] next_slot_nr Next slot number Number of the next ...
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PRELIMINARY 6.1.1.5 RAM1: ATM or AAL Receive Idle Slot Read/write Address 00200 Reset value: Not applicable. RAM must be reset and initialized via SW cont_slot Continuation slot indicator 0 = This slot is not a continuation ...
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PRELIMINARY Not used x43_scram ATM cell payload scrambling enable bling 0 = Disabled 1 = Enabled channel_ Channel mode mode 00 = Inactive mode 01 = Active mode (normal mode Standby mode 11 = ...
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PRELIMINARY 31 next_slot_nr[4:0] = 00000 Not used next_slot_nr Next slot number 0 = This field must be all 0 for ATM continuation slots ref_slot_nr Reference slot number Number of the reference slot of this channel cont_slot Continuation ...
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PRELIMINARY band_width[3:0] next_slot_nr Next slot number Number of the second slot of this channel. When no continuation slots exist, the entry “next_slot_nr” should refer to the reference slot pcfN[p_ces snp_check SNP field check enable X ...
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PRELIMINARY 1 = Enabled sdt_once SDT pointer appears once in 8 cell cycle [aal0 [sdt All cells with CSI bit = 1 and even SN are supposed to contain a ...
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PRELIMINARY pcfN[p_ces [aal0 Disabled 1 = Enabled channel_ Channel mode mode 00 = Inactive mode 01 = Active mode (normal mode Standby mode 11 = Active mode (normal ...
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PRELIMINARY next_slot_nr Next slot number Number of the next slot of this channel. When no continuation slots exist, the entry “next_slot_nr” should refer to the reference slot. slot_index Index number of the current slot pcfN[p_cas ...
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PRELIMINARY 01 = Select byte-pattern 1, defined in bp10[bp1 Select byte-pattern 2, defined in bp32[bp2 Select byte-pattern 3, defined in bp32[bp3] cont_slot Continuation slot indicator 0 = This is not a continuation slot ref_slot Reference slot ...
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PRELIMINARY starv_bpslct Starvation byte-pattern select 00 = Select byte-pattern 0, defined in bp10[bp0 Select byte-pattern 1, defined in bp10[bp1 Select byte-pattern 2, defined in bp32[bp2 Select byte-pattern 3, defined in bp32[bp3] starv_ini Number of ...
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PRELIMINARY 6.1.4.1 RAM4: AAL Transmit Conditioning Slot Read/write Address 00800 Reset value: Not applicable. RAM must be reset and initialized via SW Not used cond_down CAS conditioning nibbles in downstream for the ...
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PRELIMINARY 6.2 External RAM The IWE8 requires an external 64K MPADR[17:0] 3FFFF 64k 16 H 30000 H 2FFFF 32k 16 H 28000 Segmentation / ATM Receive Buffers H 27FFF 8128 26040 H 2603F 26020 ...
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PRELIMINARY Table 30 Statistics Counters for ATM Ports counter_nr Counter contents 2) 0 Number of discarded cells due to output queue, ATM Receive Buffer overflow 1 Number of received cells with correctable HEC errors 2 Number of received cells with ...
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PRELIMINARY Table 31 Statistics Counters for AAL Ports 4 Number of cells causing a Reassembly Buffer overflow (AAL0 & AAL1). It includes accepted cells that are causing the filling level to exceed the predefined threshold and discarded cells due to ...
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PRELIMINARY 3) If the “auto-re-initialization Reference Slot.auto_reinit_uf = 1B), the re-initialization of the Reassembly Buffer will terminate an underflow status as soon as start of underflow is detected. Thus, the underflow status for the device is no longer valid although ...
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PRELIMINARY RMADR MPADR The format of the counter threshold entries is as follows: 31 thres_act thres_act threshold ...
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PRELIMINARY For reading the Interrupt Queue refer to Each interrupt queue entry identifies a particular statistics counter that has reached its threshold value. The format of the interrupt queue entries is as follows iq_ne not used 7 ...
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PRELIMINARY The format of the timer entries is as follows timer_en 7 timer_en Timer enable The timer_en bit can be used by the SW to start/stop/pause the timer. Upon reaching timer_value = 0 the timer_en will be ...
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PRELIMINARY MPADR[17:0] 2603B H 26024 H 26023 H 26022 H 26021 H 26020 H The ATM header to be used for cell insertion has to be programmed at MPADR = 26020 . H The format of the ATM Header entry ...
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PRELIMINARY For reading the extraction buffer, refer to MPADR[17:0] 27FFF Cell #254 H · 26060 Cell #2 H 2605F H 2605A H 26059 H 26042 H 26041 H 26040 H The format of the ATM header entry is as follows: ...
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PRELIMINARY RMADR MPADR 6.2.7.1 ATM Receive Buffer The SW does not need to access the ATM Receive Buffers. 6.2.7.2 Segmentation Buffer The ATM ...
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PRELIMINARY RMADR MPADR port_nr [2:0] The SW does not need to access the Reassembly/ATM Transmit Buffers. Preliminary Data Sheet PXB4219E / PXB4220E ...
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PRELIMINARY 7 Register Description The internal registers occupy the lowest addresses. Accesses to the internal registers are 16 bit oriented. Entry size = 16 bit Note Table 32 Internal Registers MPADR Width Name 00000 + ...
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PRELIMINARY Table 32 Internal Registers MPADR Width Name 00021 16 H 00022 16 H 00023 16 H 00024 12 H 00025 5 H 00026 8 H 00027 16 H 00028 14 H 00029 16 H 0002A 16 H 0002B 4 ...
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PRELIMINARY Table 32 Internal Registers MPADR Width Name 00112 8 H 00113 6 H 00114 + 00115 + 00116 + 00117 + ...
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PRELIMINARY 7.1 Port Configuration Registers (pcfN) Read/write Address 00000 Reset value: 0000. 15 Not used p_cell_ p_thr_m[1:0] disc 7 p_srts p_slp p_ulp p_cell_disc Port Cell Discard Enable X = When p_atm = 0 or acfg.a_hec_mode = Port ...
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PRELIMINARY 1 = Enabled p_atm Port ATM mode 0 = AAL (CES) mode port 1 = ATM (PHY) mode port p_ces Port circuit emulation service X = When p_atm = 1 and for PXB 4219 version 0 = Structured (N ...
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PRELIMINARY p_rx_em Port receive emergency mode Enables the automatic switch over to emergency mode 0 = Disabled 1 = Enabled p_tx_act Port transmit activate 0 = Disabled (Framer outputs tristated Enabled p_tx_mfs Port transmit multiframe signal at pin ...
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PRELIMINARY 7.2 ASIC Configuration Register (acfg) Read/write Address 00008 Reset value: 0000 H 15 a_icrc_ a_hec_ a_hec_ dwn algor mode 7 a_dummy_rts[2:0] a_icrc_dwn ICRC power down Once the SRTS block is switched off, it can only be enabled by hardware ...
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PRELIMINARY a_crv_en Clock recovery interface enable 0 = Disabled 1 = Enabled a_dummy_ Dummy RTS value rts Dummy RTS value that will be transmitted in the first and second SRTS period after start of segmentation. a_emg_ Emergency byte-pattern select bpslct ...
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PRELIMINARY 7.3 OAM Control Register (oamc) Read/write Address 00009 Reset value: 0000 Not used tim_set1_en Timer set 1 enable 0 = Disabled 1 = Enabled dest_read Destructive read mode 0 = Disabled 1 = Enabled: OAM counter ...
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PRELIMINARY 7.4 OAM-Counter Enable Register for ATM Ports (catm) Read/write Address 0000A Reset value: 0000 Not used cnt_atm_en OAM-counter enable for ATM ports X = When pcfN[p_atm Disabled 1 = Enabled Preliminary Data ...
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PRELIMINARY 7.5 OAM-Counter Enable Register for AAL Ports (caal) Read/write Address 0000B Reset value: 0000 cnt_aal_en OAM-counter enable for AAL ports X = When pcfN[p_atm Disabled 1 = Enabled Preliminary Data Sheet PXB4219E ...
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PRELIMINARY 7.6 Byte-Pattern Register bp3 and bp2 (bp32) Read/write Address 0000C Reset value: FFFF bp3 Byte-pattern 3 bp2 Byte-pattern 2 Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E H bp3[7:0] bp2[7:0] 160 IWE8 V3.4 Register Description 8 ...
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PRELIMINARY 7.7 Byte-Pattern Register bp1 and bp0 (bp10) Read/write Address 0000D Reset value: FFFF bp1 Byte-pattern 1 bp0 Byte-pattern 0 Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E H bp1[7:0] bp0[7:0] 161 IWE8 V3.4 Register Description 8 ...
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PRELIMINARY 7.8 ATM Control Register (atmc) Read/write Address 0000E Reset value: 7655 H 15 alpha[3:0] 7 alpha Number of consecutive incorrect HEC (SYNC delta Number of consecutive correct HEC (PRESYNC coset Coset value x-ored with HEC Preliminary Data Sheet PXB4219E ...
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PRELIMINARY 7.9 RX Idle/Unassigned Cell Control Register (rxid) Read/write Address 0000F Reset value: 0101 H 15 prg_rx_hd[7:4] 7 prg_rx_hd Programmable RX idle/unassigned cell header octet 1[7:4] 00 according to I.361 H prg_rx_hd Programmable RX idle/unassigned cell header octet 4[3:0] 01 ...
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PRELIMINARY 7.10 TX Idle/Unassigned Cell Control Register (txid) Read/write Address 00010 Reset value: 016A H 15 prg_tx_hd[7:4] 7 prg_tx_hd Programmable TX idle/unassigned cell header octet 1[7:4] 00 according to I.361 H prg_tx_hd Programmable TX idle/unassigned cell header octet 4[3:0] 01 ...
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PRELIMINARY 7.11 Loopback Control Register (lpbc) Read/write Address 00011 Reset value: 0000 tulp tdlp vci_flt_ t tslp Transparent serial loop 0 = Non-transparent 1 = Transparent tulp Transparent upstream UTOPIA loop X = When pcfN[p_atm ...
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PRELIMINARY 7.12 Cell Fill Register for Partially Filled Cells (cfil) Read/write Address 00012 Reset value: 0000 cfil Dummy fill octet for partially filled cells Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E H Not used cfil[7:0] 166 ...
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PRELIMINARY 7.13 Interrupt Mask Register 1 (imr1) Read/write Address 00013 Reset value: FFFF imr1 Each bit masks the corresponding bit in isr1 0 = Not masked 1 = Masked Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E ...
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PRELIMINARY 7.14 Timer Enable Register (time) Read/write Address 00014 Reset value: 0000 tim_set2_en Timer set 2 enable 0 = Disabled 1 = Enabled Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E H Not used Not used 168 ...
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PRELIMINARY 7.15 Cell Delineation FSM Status Register (cdfs) Read only Address 00015 Reset value: 0000 H 15 status_p7[1:0] 7 status_p3[1:0] status_pN Cell Delineation FSM status of port When pcfN[p_atm Hunt 01 = Presync ...
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PRELIMINARY 7.16 Version Register (vers) Read only Address 00016 e1/t1 mtypsel Microcontroller type select 0 = Microcontroller Interface runs in Intel Mode 1 = Microcontroller Interface runs in Motorola Mode ec Status of EC pin 0 = ...
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PRELIMINARY 7.17 Clock Monitor Register (ckmo) Read only Address 00017 Reset value: 0000 frclk_failure FRCLK clock failure on port N Bit remains active only as long as a clock failure on FRCLK is detected False ...
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PRELIMINARY 7.18 Interrupt Status Register 1 (isr1) Read only, Address 00018 Reset value: 0000 H 15 iq_ne eis4 7 Not used ut_soc ut_par iq_ne Interrupt queue not empty 0 = False 1 = True eis4 A bit is set in ...
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PRELIMINARY ut_par Parity error on UTOPIA bus ex_par Parity error on external RAM In order to prevent external RAM parity errors, the external RAM should be written completely during board initialization by the microprocessor False 1 = True ...
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PRELIMINARY 7.19 Extended Interrupt Status 1 Register (eis1) Destructive read Address 00019 Reset value: 0000 cf_fifo_full Cell filter FIFO full 0 = False 1 = True cf_fifo_n_ Cell filter FIFO not empty empty 0 = False 1 ...
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PRELIMINARY 7.20 Extended Interrupt Status 2 Register (eis2) Destructive read Address 0001A Reset value: 0000 rts_overflow RTS buffer overflow of IWE core at port N Applicable for AAL ports in unstructured CES mode with SRTS ...
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PRELIMINARY 7.21 Extended Interrupt Status 3 Register (eis3) Destructive read Address 0001B Reset value: 0000 tim_set1_ Timer of set 1 expired exp Each bit indicates if the corresponding timer expired 0 = False 1 = True Preliminary ...
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PRELIMINARY 7.22 Extended Interrupt Status 4 Register (eis4) Destructive read Address 0001C Reset value: 0000 ocd_end End of OCD (Out of cell delineation) state at port When pcfN[p_atm False 1 ...
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PRELIMINARY 7.23 Interrupt Status Register 2 (isr2) Destructive read Address 0001D Reset value: 0000 tim_set2_ Timer of timer set 2 expired exp Each bit indicates if the corresponding timer expired 0 = False 1 = True ...
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PRELIMINARY 7.24 Operation Mode Register (opmo) Read/write Address 0001E Reset value 1100 H 15 Not used symn 7 bufthr0 tfpp symn SYMn mode This bit is relevant only in SYM2 and SYM8 0 = FRMFB[0] is used for frame and ...
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PRELIMINARY 1 = FRMFB is active high ftri Framer transmit rising edge valid for GIM 0 = FTDAT outputs are clocked with the falling edge of FTCKO 1 = FTDAT outputs are clocked with the rising edge of FTCKO frri ...
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PRELIMINARY 7.25 FT Clock Select Register (ftcs) Read/write Address 0001F Reset value 0000 H 15 ftck7[1:0] 7 ftck3[1:0] ftck Clock Source for framer transmit interface i valid for FAM and GIM 00 = FTCKO Recovered Clock of ICRC if opmo[rts_eval] ...
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PRELIMINARY 7.26 Cell Filter VCI Pattern 1 Register (cfvp1) Read/write Address 20 H Reset value: 0000 vci_pattern1 First VCI pattern the cell header is compared with. Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E vci_pattern1[15:8] vci_pattern1[7:0] 182 ...
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PRELIMINARY 7.27 Cell Filter VCI Mask 1 Register (cfvm1) Read/write Address 00021 Reset value: 0000 vci_mask1 Each bit masks the corresponding bit in cfvp1 0 = Not masked 1 = Masked Preliminary Data Sheet PXB4219E / PXB4220E ...
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PRELIMINARY 7.28 Cell Filter VCI Pattern 2 Register (cfvp2) Read/write Address 00022 Reset value: 0000 vci_pattern2 Second VCI pattern the cell header is compared with. Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E H vci_pattern2[15:8] vci_pattern2[7:0] 184 ...
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PRELIMINARY 7.29 Cell Filter VCI Mask 2 Register (cfvm2) Read/write Address 00023 Reset value: 0000 vci_mask2 Each bit masks the corresponding bit in cfvp2 0 = Not masked 1 = Masked Preliminary Data Sheet PXB4219E / PXB4220E ...
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PRELIMINARY 7.30 Cell Filter Payload Type Register (cfpt) Read/write Address 00024 Reset value: 0000 H 15 Not used 7 pt_mask2[1:0] pt_mask1 Each bit masks the corresponding bit in pt_pattern1 Not masked 1 = Masked pt_pattern1 First PT pattern ...
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PRELIMINARY 7.31 Command Register (cmd) Read/write Address 00025 Reset value 0000 Not used vci1_comp VCI comparison corresponding to register cfvp1 and cfvm1 Disabled 1 = Enabled vci2_comp VCI comparison corresponding to register cfvp2 and cfvm2. ...
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PRELIMINARY 7.32 Cell Filter Read Pointer Register (cfrp) Read/write Address 00026 Reset value 0002 rdptr Read Pointer for the Cell Extraction Buffer 02 This value is a pointer to the current address, at which the H to ...
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PRELIMINARY 7.33 Threshold Register (thrshld) Read/write Address 00027 Reset value 00FF threshold Global ATM transmit buffer threshold for discarding cells 00 If the amount of cells stored in the ATM transmit buffer crosses H to this value ...
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PRELIMINARY 7.34 UTOPIA Configuration Register (utconf) Read/write Address 00028 Reset value 0001 H 15 Not used 7 utbaseadr[2:0] utrange UTOPIA Port Range Controls the supported port range if the device is configured as UTOPIA level 2 PHY-Layer (utlevel=0, utmaster=0, mapping_mode=000 ...
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PRELIMINARY mapping Mapping of the “port_nr” associated with the currently transferred cell _mode into the UTOPIA datastream 000 = Disabled 001 = Mapping to UDF[2:0] field in ATM header 010 = Mapping toVCI[7:5] field in ATM header 011 = Mapping ...
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PRELIMINARY 7.35 CAS 1 Register (cas1) Read/write Address 00029 Reset value: BBBB H 15 cas0port3[3:0] 7 cas0port1[3:0] cas0port0 E1 CAS frame 0 pattern for port 0 (unused in T1 mode) cas0port1 E1 CAS frame 0 pattern for port 1 (unused ...
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PRELIMINARY 7.36 CAS 2 Register (cas2) Read/write Address 0002A Reset value: BBBB H 15 cas0port7[3:0] 7 cas0port5[3:0] cas0port4 E1 CAS frame 0 pattern for port 4 (unused in T1 mode) cas0port5 E1 CAS frame 0 pattern for port 5 (unused ...
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PRELIMINARY 7.37 CAS 3 Register (cas3) Read/write Address 0002B Reset value: 000D Not used cas_idle CAS idle pattern for unused timeslots of the Tx frame Preliminary Data Sheet PXB4219E / PXB4220E / PXB4221E H Not used 194 ...
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PRELIMINARY 7.38 Threshold Register for Ports 0 and 1 (thrsp01) Read/write Address 0002C Reset value: FFFF p_odd Port 1 threshold for backpressure of UTOPIA Tx p_even Port 0 threshold for backpressure of UTOPIA Tx Preliminary Data Sheet ...
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PRELIMINARY 7.39 Threshold Register for Ports 2 and 3 (thrsp23) Read/write Address 0002D Reset value: FFFF p_odd Port 3 threshold for backpressure of UTOPIA Tx p_even Port 2 threshold for backpressure of UTOPIA Tx Preliminary Data Sheet ...
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PRELIMINARY 7.40 Threshold Register for Ports 4 and 5 (thrsp45) Read/write Address 02E Reset value: FFFF p_odd Port 5 threshold for backpressure of UTOPIA Tx p_even Port 4 threshold for backpressure of UTOPIA Tx Preliminary Data Sheet ...
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PRELIMINARY 7.41 Threshold Register for Ports 6 and 7 (thrsp67) Read/write Address 0002F Reset value: FFFF p_odd Port 7 threshold for backpressure of UTOPIA Tx p_even Port 6 threshold for backpressure of UTOPIA Tx Preliminary Data Sheet ...
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PRELIMINARY 7.42 Extended Interrupt Status 0 Register (eis0) Destructive Read Address 00030 Reset value: 0000 lcd_end End of LCD detect on port False 1 = True lcd_start Start of LCD detect on port N ...
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PRELIMINARY 7.43 LCD Timer Register (lcdtimer) Read/write Address 00031H Reset value: FFFF lcd_val LCD timer preload value The port specific LCD timer is pre-loaded with 128 * lcd_val and clocked with CLOCK. After expiration an interrupt is ...