AT32UC3A0256AU Atmel Corporation, AT32UC3A0256AU Datasheet - Page 156

• Manufacturer Part Number: AT32UC3A0256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
21.4.9
21.4.10
21.5
21.5.1
Table 21-1.
21.5.2
Offset
0x0C
0x1C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
User Interface
0x00C0 - 0x00FF
0x0000 - 0x003F
0x0040 - 0x007F
0x0080 - 0x00BF
0x0100 - 0x013F
Address Range
Priority
Error Handling
Memory Map Overview
Channel Memory Map
Register Map Overview
-
-
Memory Address Reload Register
Transfer Counter Reload Register
If more then one PDCA channel is requesting transfer at a given time, the PDCA channels are
prioritized by their channel number. Channels with lower numbers have priority over channels
with higher numbers, giving channel 0 the highest priority.
If the memory address is set to point to an invalid location in memory, an error will occur when
the PDCA tries to perform a transfer. When an error occurs, the Transfer Error flag (TERR) in
the Interrupt Status Register will be set and the DMA channel that caused the error will be
stopped. In order to restart the channel, the user must program the Memory Address Register to
a valid address and then write the Error Clear bit (ECLR) in the Control Register (CR) to ‘1’. An
interrupt can optionally be triggered on errors by writing the TERR-bit in the Interrupt Enable
Register (IER) to ‘1’.
Note:
Memory Address Register
Peripheral Select Register
Transfer Counter Register
Interrupt Enable Register
Control Register
Status Register
Mode Register
The number of channels is implementation specific. See part documentation for details.
Register
DMA channel n-1 configuration registers
DMA channel 0 configuration registers
DMA channel 1 configuration registers
DMA channel 2 configuration registers
DMA channel 3 configuration registers
DMA channel 4 configuration registers
Register Name
MARR
TCRR
MAR
PSR
TCR
MR
IER
CR
SR
Contents
-
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Write-only
Write-only
Access
AT32UC3A
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
*
-
-
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