AT32UC3A0256AU Atmel Corporation, AT32UC3A0256AU Datasheet - Page 401

• Manufacturer Part Number: AT32UC3A0256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
Figure 27-35. Page Mode Read Protocol (Address MSB and LSB are defined in
27.6.9.2
A[MSB]
D[15:0]
A[LSB]
CLK_SMC
NRD
NCS
Byte Access Type in Page Mode
The NRD and NCS signals are held low during all read transfers, whatever the programmed val-
ues of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS
timings are identical. The pulse length of the first access to the page is defined with the
NCS_RD_PULSE field of the PULSE register. The pulse length of subsequent accesses within
the page are defined using the NRD_PULSE parameter.
In page mode, the programming of the read timings is described in
Table 27-6.
The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE
timings as page access timing (t
the programmed value for t
The Byte Access Type configuration remains active in page mode. For 16-bit or 32-bit page
mode devices that require byte selection signals, configure the BAT field of the REGISTER to 0
(byte select access type).
Parameter
READ_MODE
NCS_RD_SETUP
NCS_RD_PULSE
NRD_SETUP
NRD_PULSE
NRD_CYCLE
NCS_RD_PULSE
Programming of Read Timings in Page Mode
t
pa
Value
‘x’
‘x’
t
‘x’
t
‘x’
pa
sa
pa
is shorter than the programmed value for t
pa
) and the NRD_PULSE for accesses to the page (t
Definition
No impact
No impact
Access time of first access to the page
No impact
Access time of subsequent accesses in the page
No impact
NRD_PULSE
t
sa
Table
27-5)
NRD_PULSE
t
sa
Table
sa
.
27-6:
AT32UC3A
sa
), even if
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