AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 102

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.14.4
9.2.14.5
32002F–03/2010
Debug Communication Emulator Register (DCEMU)
Debug Communication Status Register (DCSR)
Communication Status Register. The emulator should poll the status register and read DCCPU if
the dirty bit is set.
Table 9-7.
When the emulator writes to this register, a dirty bit is set in the Debug Communication Status
register. The CPU can poll this bit to see if DCEMU contains unread data..
Table 9-8.
To avoid overruns the CPU must poll this register before writing a new value to DCCPU. Note
that the bits in this register are not automatically cleared in OCD mode. This allows a debugger
to update views and observe the system without accidentally modifying the DCSR register.
The OCD system can produce interrupts when the DCEMU register has been updated and when
the DCCPU register is read. The CPURI and EMUDI flags are set on the interrupt events, but
are cleared by software by writing the DCSR register. To enable the interrupts the corresponding
bits in the DCCR register has to be set and the Interrpt controller has to be programmed.
Table 9-9.
R/W
R/W
R/W
R/W
R/W
R
R/W
Bit Number
31:0
Bit Number
31:0
Bit Number
31:4
1
Debug Communication CPU Register
Debug Communication Emulator Register
Debug Communication Status Register
Field Name
DATA
Field Name
DATA
Field Name
Reserved
EMUDI
Init. Val.
0x0000_
0000
Init. Val.
0x0000_
0000
Init. Val.
0x0000_
0000
0
Description
Data Value
Data written by CPU
Description
Data Value
Data written by Emulator
Description
Reserved
These bits are reserved, and will always read as 0
Emulator Data Dirty Interrupt flag
0 = DCEMU has not been written to since the
clearing of this bit.
1 = DCEMU contains a new data value.
This bit is cleared by writing this bit to 0.
AVR32
102