AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 138

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.8
9.8.1
9.8.1.1
32002F–03/2010
Memory Service Unit
CRC
Starting CRC calculation
The tool can read and write this register, although it is recommended that only the CPU writes
this register.
Table 9-53.
The Memory Service Unit (MSU) provides access to complex memory operations, such as CRC
checking and NanoTrace. The MSU is accessed by SAB registers, but these are not mapped
into the OCD register space, and needs to be accessed with MEMORY_WORD_ACCESS or
MEMORY_SERVICE_ACCESS JTAG commands. In addition the MSU registers are mapped in
the system register space and are available tothe CPU. Refer to
on page 11
The MSU can calculate a Cyclic Redundancy Check (CRC) value for a memory area. The algo-
rithm used is the industry standard CRC32 algorithm using the generator polynomial
0xEDB88320.
To calculate CRC for a memory range, you need to write the start address into the ADDRHI and
ADDRLO registers, and the size of the memory range into the LENGTH register. Both the start
address and the length must be word aligned.
The initial value used for the CRC calculation must be written to the DATA register. This value
will usually be 0xFFFFFFFF, but can be e.g. the result of a previous CRC calculation if generat-
ing a common CRC of separate memory blocks.
Once completed, the calculated CRC value can be read out of the DATA register. The read
value must be inverted to match standard CRC32 implementations, or kept non-inverted if used
as starting point for subsequent CRC calculations.
If the device has enabled protection features, e.g. the protection fuse has been set on devices
with onboard flash memory, it is only possible to calculate CRC on a predefined memory area. In
most cases this area will be the entire onboard flash memory. The ADDRHI, ADDRLO,
LENGTH, and DATA registers will be forced to predefined values once the CRC operation is
started, and user-written values are ignored. This allows the user to verify the contents of a pro-
tected device, while denying malicious users the option of analyzing the memory contents
through selective CRC calculations.
The actual test is started by writing OP_CRC to the CTRL register. A running CRC operation can
be cancelled by writing OP_IDLE to CTRL.
R/W
RW
Bit Number
31:0
for details.
Ownership Trace Process ID (PID)
Field Name
PROCESS
Init. Val.
0
Description
PROCESS - Process ID
The unique Process ID number of the currently
running process.
Section 2.5 ”System registers”
AVR32
138