AT32UC3A1512 Atmel Corporation, AT32UC3A1512 Datasheet - Page 641

• Manufacturer Part Number: AT32UC3A1512
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1512

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
31.4
31.5
31.5.1
31.5.2
31.5.3
31.5.4
31.6
31.6.1
31.6.1.1
31.6.1.2
Pin Name List
Product Dependencies
Functional Description
I/O Lines
Debug operation
Power Management
Interrupt
TC Description
16-bit Counter
Clock Selection
Table 31-2.
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
The programmer must first program the PIO controllers to assign the TC pins to their peripheral
functions.
The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps
peripherals running in debug operation.
The Timer Counter clock is generated by the power manager. Before using the TC, the program-
mer must ensure that the TC clock is enabled in the power manager.
The TC has an interrupt line connected to the interrupt controller. Handling the TC interrupt
requires programming the interrupt controller before configuring the TC.
The three channels of the Timer Counter are independent and identical in operation. The regis-
ters for channel programming are listed in
Each channel is organized around a 16-bit counter. The value of the counter is incremented at
each positive edge of the selected clock. When the counter has reached the value 0xFFFF and
passes to 0x0000, an overflow occurs and the COVFS bit in SR (Status Register) is set.
The current value of the counter is accessible in real time by reading the Counter Value Regis-
ter, CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000
on the next valid edge of the selected clock.
At block level, input clock signals of each channel can either be connected to the external inputs
TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0, TIOA1 or
TIOA2 for chaining by programming the BMR (Block Mode). See
Pin Name
TCLK0-TCLK2
TIOA0-TIOA2
TIOB0-TIOB2
TC pin list
External Clock Input
I/O Line A
I/O Line B
Description
Table 31-4 on page
654.
Figure
Type
Input
I/O
I/O
31-2.
AT32UC3A
641