AT32UC3A464S Atmel Corporation, AT32UC3A464S Datasheet - Page 204

• Manufacturer Part Number: AT32UC3A464S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464S

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

204
AVR32
LSL – Logical Shift Left
Architecture revision:
Architecture revision1 and higher.
Description
Shifts all bits in a register the amount of bits specified to the left. The shift amount can reside in
a register or be specified as an immediate. Zeros are shifted into the LSBs. The last bit that is
shifted out is placed in C.
Operation:
I.
II.
III.
Syntax:
I.
II.
III.
Operands:
I.
II.
III.
Status Flags:
Opcode:
Rd ← LSL(Rx, Ry[4:0]);
Rd ← LSL(Rd, sa5);
Rd ← LSL(Rs, sa5);
lsl
lsl
lsl
{d, x, y} ∈ {0, 1, …, 15}
d ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}
{d,s} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}
Format I: Shamt = Ry[4:0], Op = Rx
Format II: Shamt = sa5, Op = Rd
Format III: Shamt = sa5, Op = Rs
Q:
V:
N:
Z:
C:
Rd, Rx, Ry
Rd, sa
Rd, Rs, sa
Not affected
Not affected
N ← RES[31]
Z ← (RES[31:0] == 0)
if Shamt != 0
else
C ← Op[32-Shamt]
C ← 0
32000D–04/2011