AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 115
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AT32UC3C1512C
Manufacturer Part Number
AT32UC3C1512C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1512C
Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3C1512C
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3C1512C-AUR
Manufacturer:
Atmel
Quantity:
1 402
Part Number:
AT32UC3C1512C-AUR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3C1512C-AZR
Manufacturer:
ATMEL
Quantity:
1 000
Company:
Part Number:
AT32UC3C1512C-AZT
Manufacturer:
ATMEL
Quantity:
1 000
Part Number:
AT32UC3C1512C-AZT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3C1512C-U
Manufacturer:
ATMEL
Quantity:
997
Part Number:
AT32UC3C1512C-Z
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Table 9-10.
32000D–04/2011
ld.sh
ld.sh{cond4}
ld.w
ld.w{cond4}
ld.d
ldins.b
ldins.h
ldswp.sh
ldswp.uh
ldswp.w
lddpc
lddsp
Load/Store Operations (Continued)
C
C
C
E
E
E
C
C
C
E
E
E
E
C
C
C
E
E
E
E
E
E
E
C
C
Rd, Rp++
Rd, --Rp
Rd, Rp[disp]
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd, Rp[disp]
Rd, Rp++
Rd, --Rp
Rd, Rp[disp]
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd, Rb[Ri:<part> <<
2]
Rd, Rp[disp]
Rd, Rp++
Rd, --Rp
Rd, Rp
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd:<part>, Rp[disp]
Rd:<part>, Rp[disp]
Rd, Rp[disp]
Rd, PC[disp]
Rd, SP[disp]
Load signed halfword with post-
increment.
Load signed halfword with pre-decrement.
Load signed halfword with displacement.
Indexed Load signed halfword.
Load signed halfword with displacement if
condition satisfied.
Load word with post-increment.
Load word with pre-decrement.
Load word with displacement.
Indexed Load word.
Load word with extracted index into Rd.
Load word with displacement if condition
satisfied.
Load doubleword with post-increment.
Load doubleword with pre-decrement.
Load doubleword.
Load double with displacement.
Indexed Load double.
Load byte with displacement and insert at
specified byte location in Rd.
Load halfword with displacement and
insert at specified halfword location in Rd.
Load halfword with displacement, swap
bytes and sign-extend
Load halfword with displacement, swap
bytes and zero-extend
Load word with displacement and swap
bytes.
Load with displacement from PC.
Load with displacement from SP.
Rd ← SE(*(Rp++))
Rd ← SE(*(--Rp))
Rd ← SE(*(Rp+(ZE(disp3)<<1)))
Rd ← SE(*(Rp+(SE(disp16))))
Rd ← SE(*(Rb+(Ri << sa2)))
if {cond4}
Rd ← SE(*(Rp+ZE(disp9<<1)))
Rd ← *(Rp++)
Rd ← *(--Rp)
Rd ← *(Rp+(ZE(disp5)<<2))
Rd ← *(Rp+(SE(disp16)))
Rd ← *(Rb+(Ri << sa2))
Rd ← *(Rb+(Ri:<part> << 2))
if {cond4}
Rd ← *(Rp+ZE(disp9<<2))
Rd+1:Rd ← (*(Rp++))
Rd+1:Rd ← (*(--Rp))
Rd+1:Rd ← *(Rp)
Rd+1:Rd ← *(Rp+SE(disp16))
Rd+1:Rd ← *(Rb+(Ri << sa2))
Rd:<part>← *(Rp+(SE(disp12)))
Rd:<part> ←
*(Rp+(SE(disp12)<<1))
Temp ← *(Rp+(SE(disp12) << 1)
Rd ← SE(Temp[7:0], Temp[15:8])
Temp ← *(Rp+(SE(disp12) << 1)
Rd ← ZE(Temp[7:0], Temp[15:8])
Temp ← *(Rp+(SE(disp12) << 2)
Rd[31:24] ← Temp[7:0],
Rd[23:16] ← Temp[15:8],
Rd[15:8] ← Temp[23:16],
Rd[7:0] ← Temp[31:24]
Rd ← *((PC && 0xFFFF_FFFC)
+(ZE(disp7)<<2))
Rd ← *((SP && 0xFFFF_FFFC)
+(ZE(disp7)<<2))
AVR32
1
1
1
1
1
2
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
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