AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 36
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AT32UC3C1512C
Manufacturer Part Number
AT32UC3C1512C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1512C
Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3C1512C
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3C1512C-AUR
Manufacturer:
Atmel
Quantity:
1 402
Part Number:
AT32UC3C1512C-AUR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3C1512C-AZR
Manufacturer:
ATMEL
Quantity:
1 000
Company:
Part Number:
AT32UC3C1512C-AZT
Manufacturer:
ATMEL
Quantity:
1 000
Part Number:
AT32UC3C1512C-AZT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3C1512C-U
Manufacturer:
ATMEL
Quantity:
997
Part Number:
AT32UC3C1512C-Z
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Table 5-1.
36
Virtual
address
[31:29]
111
110
101
100
0xx
AVR32
Segment
name
P4
P3
P2
P1
P0 / U0
The virtual address map
The P3 space is also by default segment translated to the physical address range 0x00000000
to 0x1FFFFFFF. By enabling and setting up the MMU, the P3 space becomes page translated.
Page translation will override segment translation.
The P4 space is intended for memory mapping special system resources like the memory arrays
in caches. This segment is non-cacheable, non-translated.
The U0 segment is accessible in the unprivileged user mode. This segment is cacheable and
translated, depending upon the configuration of the cache and the memory management unit. If
accesses to other memory addresses than the ones within U0 is made in application mode, an
access error exception is issued.
The virtual address map is summarized in
The segment translation can be disabled by clearing the S bit in the MMUCR. This will place all
the virtual memory space into a single 4 GB mapped memory space. Doing this will give all
access permission control to the AP bits in the TLB entry matching the virtual address, and allow
all virtual addresses to be translated. Segment translation is enabled by default.
The AVR32 architecture has two translations of addresses.
Both these translations are performed by the MMU and they can be applied independent of each
other. This means that you can enable:
The segment translation is by default turned on and the page translation is by default turned off
after reset. The segment translation is summarized in
Virtual
Address Range
0xFFFF_FFFF to
0xE000_0000
0xDFFF_FFFF to
0xC000_0000
0xBFFF_FFFF to
0xA000_0000
0x9FFF_FFFF to
0x8000_0000
0x7FFF_FFFF to
0x0000_0000
1. Segment translation (enabled by the MMUCR[S] bit)
2. Page translation (enabled by the MMUCR[E] bit)
1. No translation. Virtual and physical addresses are the same.
2. Segment translation only. The virtual and physical addresses are the same for
3. Page translation only. All addresses are mapped as described by the TLB entries.
4. Both segment and page translations. P1 and P2 are mapped to the physical address
addresses residing in the P0, P4 and U0 segments. P1, P2 and P3 are mapped to the
physical address range 0x00000000 to 0x1FFFFFFF.
range 0x00000000 to 0x1FFFFFFF. U0, P0 and P3 are mapped as described by the
TLB entries. The virtual and physical addresses are the same for addresses residing in
the P4 segment.
Segment
size
512 MB
512 MB
512 MB
512 MB
2 Gb
Accessible
from
Privileged
Privileged
Privileged
Privileged
Unprivileged
Privileged
Table 5-1 on page
Yes
Yes
Default
segment
translated
No
Yes
No
Figure 5-2 on page
36.
Characteristics
System space
Unmapped, Uncacheable
Mapped,
Cacheable
Unmapped, Uncacheable
Unmapped, Cacheable
Mapped, Cacheable
37.
32000D–04/2011