AT32UC3C2128C Atmel Corporation, AT32UC3C2128C Datasheet - Page 10
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AT32UC3C2128C
Manufacturer Part Number
AT32UC3C2128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2128C
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2128C-A2UR
Manufacturer:
ATMEL
Quantity:
1 043
Part Number:
AT32UC3C2128C-Z2UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
32002F–03/2010
EM - Exception mask
I3M - Interrupt level 3 mask
I2M - Interrupt level 2 mask
I1M - Interrupt level 1 mask
I0M - Interrupt level 0 mask
GM - Global Interrupt Mask
Table 2-1.
When this bit is set, exceptions are masked. Exceptions are enabled otherwise. The bit is auto-
matically set when exception processing is initiated or Debug Mode is entered. Software may
clear this bit after performing the necessary measures if nested exceptions should be supported.
This bit is set at reset.
When this bit is set, level 3 interrupts are masked. If I3M and GM are cleared, INT3 interrupts
are enabled. The bit is automatically set when INT3 processing is initiated. Software may clear
this bit after performing the necessary measures if nested INT3s should be supported. This bit is
cleared at reset.
When this bit is set, level 2 interrupts are masked. If I2M and GM are cleared, INT2 interrupts
are enabled. The bit is automatically set when INT3 or INT2 processing is initiated. Software
may clear this bit after performing the necessary measures if nested INT2s should be supported.
This bit is cleared at reset.
When this bit is set, level 1 interrupts are masked. If I1M and GM are cleared, INT1 interrupts
are enabled. The bit is automatically set when INT3, INT2 or INT1 processing is initiated. Soft-
ware may clear this bit after performing the necessary measures if nested INT1s should be
supported. This bit is cleared at reset.
When this bit is set, level 0 interrupts are masked. If I0M and GM are cleared, INT0 interrupts
are enabled. The bit is automatically set when INT3, INT2, INT1 or INT0 processing is initiated.
Software may clear this bit after performing the necessary measures if nested INT0s should be
supported. This bit is cleared at reset.
When this bit is set, all interrupts are disabled. This bit overrides I0M, I1M, I2M and I3M. The bit
is automatically set when exception processing is initiated, Debug Mode is entered, or a Java
trap is taken. This bit is automatically cleared when returning from a Java trap. This bit is set
after reset.
M2
1
1
1
1
0
0
0
0
Mode bit settings
M1
1
1
0
0
1
1
0
0
M0
1
0
1
0
1
0
1
0
Mode
Non Maskable Interrupt
Exception
Interrupt level 3
Interrupt level 2
Interrupt level 1
Interrupt level 0
Supervisor
Application
AVR32
10