AT32UC3C2128C Atmel Corporation, AT32UC3C2128C Datasheet - Page 99
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
AT32UC3C2128C
Manufacturer Part Number
AT32UC3C2128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2128C
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2128C-A2UR
Manufacturer:
ATMEL
Quantity:
1 043
Part Number:
AT32UC3C2128C-Z2UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
9.2.12
32002F–03/2010
OCD Interrupts
rently executing mode, only PID and DCCPU can be written. Illegal access to the registers will
be ignored with no error reporting.
Table 9-3.
To support custom debug protocols running in software the OCD system support giving inter-
rupts to the CPU when DCEMU is written or when DCCPU is read. A software protocol handler
can then be triggered by these interrupts instead of having to poll DCSR to see if the data in
DCCPU or DCEMU has been read or written.
To enable these interrupts the user must do the following:
Register
Development Control (DC)
Watchpoint Trigger (WT)
Data Trace Control (DTC)
Data Trace Start Address (DTSA) Channel 1 to
2
Data Trace End Address (DTEA) Channel 1 to
2
PC Breakpoint/Watchpoint Control (BWC)
Data Breakpoint/Watchpoint Control (BWC)
PC Breakpoint/Watchpoint Address (BWA)
Data Breakpoint/Watchpoint Address (BWA)
Breakpoint/Watchpoint Data (BWD)
Ownership Trace Process ID (PID)
Debug Instruction Register
Debug Program Counter
Debug Communication CPU (DCCPU)
Debug Communication Emulator (DCEMU)
• Program the interrupt controller with the correct priority and handler address for the interrupt.
• Enable the interrupts from the OCD by setting the corresponding bits in DCCR
OCD Register access
Can be written by JTAG
while CPU is running?
Yes
Yes
Can be written to disable /
enable trace channels.
Can only be written while
trace channel is disabled
Can only be written while
trace channel is disabled
Can be written to disable /
enable watchpoints /
breakpoints.
Can be written to disable /
enable watchpoints /
breakpoints.
Can only be written while
breakpoint / watchpoint is
disabled
Can only be written while
breakpoint / watchpoint is
disabled
Can only be written while
breakpoint / watchpoint is
disabled
Yes
No
No
Yes
Yes
Can be written by
CPU in Monitor
Mode?
Yes
Yes
Yes
Yes
Yes
Yes, if SR:DM is set.
Yes, if SR:DM is set.
Yes, if SR:DM is set
or breakpoint
disabled.
Yes, if SR:DM is set
or breakpoint
disabled.
Yes, if SR:DM is set
or breakpoint
disabled.
No
No
Yes
Yes
Yes
AVR32
99