AT32UC3C2128C Atmel Corporation, AT32UC3C2128C Datasheet - Page 33
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AT32UC3C2128C
Manufacturer Part Number
AT32UC3C2128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2128C
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2128C-A2UR
Manufacturer:
ATMEL
Quantity:
1 043
Part Number:
AT32UC3C2128C-Z2UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- Current page: 33 of 377
- Download datasheet (5Mb)
4.3
32000D–04/2011
Details on Secure State implementation
Figure 4-2.
Refer to the Technical Reference manual for the CPU core you are using for details on the
Secure State implementation.
Application
Bit 31
SP_APP
FINTPC
INT0PC
INT1PC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
Supervisor
Bit 31
RAR_SUP
RSR_SUP
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
Register File in AVR32B with secure context
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
INT0
Bit 31
LR / LR_INT0
(implementation
RAR_INT0
RSR_INT0
registers
SP_SYS
banked
defined)
PC
SR
Bit 0
INT1
Bit 31
LR / LR_INT1
(implementation
RSR_INT1
RAR_INT1
registers
SP_SYS
banked
defined)
PC
SR
Bit 0
INT2
Bit 31
LR / LR_INT2
(implementation
RSR_INT2
RAR_INT2
registers
SP_SYS
banked
defined)
PC
SR
SS_STATUS
SS_SP_APP
Bit 0
SS_SP_SYS
SS_ADRR
SS_ADRF
SS_ADR0
SS_ADR1
SS_RAR
SS_RSR
INT3
Bit 31
LR / LR_INT3
(implementation
RSR_INT3
RAR_INT3
registers
SP_SYS
banked
defined)
PC
SR
Bit 0
Exception
Bit 31
SP_SYS
RSR_EX
RAR_EX
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
NMI
Bit 31
RSR_NMI
RAR_NMI
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
AVR32
Secure
Bit 31
SP_SEC
SS_RSR
SS_RAR
FINTPC
INT0PC
INT1PC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
33
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