AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 255

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32000D–04/2011
PACKSH.{UB/SB} – Pack Signed Halfwords to Bytes
Architecture revision:
Architecture revision1 and higher.
Description
Pack the four signed halfwords located in the two source registers into four bytes in the destina-
tion register. Each of the signed halfwords are saturated to unsigned (packsh.ub) or signed bytes
(packsh.sb).
Operation:
I.
II.
Syntax:
I.
II.
Operands:
I, II.
Status Flags:
Opcode:
31
31
1
1
15
0
15
0
Rd[31:24] ← SATSU(Rx[31:16], 8); Rd[23:16] ← SATSU(Rx[15:0], 8);
Rd[15:8] ← SATSU(Ry[31:16], 8); Rd[7:0] ← SATSU(Ry[15:0], 8);
Rd[31:24] ← SATS(Rx[31:16], 8); Rd[23:16] ← SATS(Rx[15:0], 8);
Rd[15:8] ← SATS(Ry[31:16], 8); Rd[7:0] ← SATS(Ry[15:0], 8);
packsh.ub
packsh.sb
{d, x, y} ∈ {0, 1, …, 15}
Q:
V:
N:
Z:
C:
Format I:
Format II:
1
1
0
0
29
29
1
1
1
1
Flag set if saturation occured in one or more of the partial operations.
Not affected.
Not affected.
Not affected.
Not affected.
28
28
0
0
Rd, Rx, Ry
Rd, Rx, Ry
0
0
Rx
Rx
1
1
25
25
0
0
24
0
24
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
4
4
20
0
20
0
0
1
3
3
19
19
Ry
Ry
Rd
Rd
AVR32
0
0
16
16
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