AT32UC3L016 Atmel Corporation, AT32UC3L016 Datasheet - Page 42

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AT32UC3L016

Manufacturer Part Number
AT32UC3L016
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3L016

Flash (kbytes)
16 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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7.4
7.5
32099G–06/2011
Maximum Clock Frequencies
Power Consumption
Table 7-3.
Note:
These parameters are given in the following conditions:
• V
• Temperature = -40°C to 85°C
Table 7-4.
The values in
tions, except where noted:
• Operating conditions internal core supply
Symbol
V
V
V
V
Symbol
f
f
f
f
f
f
f
f
f
CPU
PBA
PBB
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
VDDIO
VDDIN
VDDCORE
VDDANA
VDDCORE
– V
– V
VDDIN
VDDCORE
1. These values are based on simulation and characterization of other AVR microcontrollers
manufactured in the same process technology. These values are not covered by test limits in
production.
= 1.62V to 1.98V
Parameter
DC supply peripheral I/Os
DC supply peripheral I/Os
and internal regulator
DC supply core
Analog supply voltage
= 3.0V
Parameter
CPU clock frequency
PBA clock frequency
PBB clock frequency
GCLK0 clock frequency
GCLK1 clock frequency
GCLK2 clock frequency
GCLK3 clock frequency
GCLK4 clock frequency
GCLK5 clock frequency
Table 7-5
Supply Rise Rates and Order
Clock Frequencies
= 1.62V, supplied by the internal regulator
are measured values of power consumption under the following condi-
GLOC
Conditions
DFLLIF main reference, GCLK0
pin
DFLLIF dithering and ssg
reference, GCLK1 pin
AST, GCLK2 pin
PWMA, GCLK3 pin
CAT, ACIFB, GCLK4 pin
0.002
Min
0
0
0
(Figure
(1)
7-1) - this is the default configuration
Max
2.5
2.5
2.5
2.5
AT32UC3L016/32/64
V/µs
V/µs
V/µs
V/µs
Unit
Rise Rate
Slower rise time requires
external power-on reset
circuit.
Rise before or at the same
time as VDDIO
Rise together with
VDDCORE
Min
Comment
Max
150
150
110
110
50
50
50
80
80
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
42

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