AT89LP2052 Atmel Corporation, AT89LP2052 Datasheet - Page 27

no-image

AT89LP2052

Manufacturer Part Number
AT89LP2052
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89LP2052

Flash (kbytes)
2 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
15
Spi
1
Uart
1
Sram (kbytes)
0.25
Operating Voltage (vcc)
2.4 to 5.5
Timers
2
Isp
SPI
Watchdog
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89LP2052-16SI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT89LP2052-16SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT89LP2052-16XU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT89LP2052-20PU
Manufacturer:
ON
Quantity:
340
Part Number:
AT89LP2052-20XI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT89LP2052-ES-18
Manufacturer:
ON
Quantity:
6 219
Part Number:
AT89LP2052-ES-2
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Table 16-1.
3547J–MICRO–10/09
Bit
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TCON = 88H
Bit Addressable
TF1
Function
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to
interrupt routine.
Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off.
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to
interrupt routine.
Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on/off.
Interrupt 1 flag. When IT1 is set, IE1 is set by hardware when the external interrupt falling edge is detected, and is cleared
by hardware when the CPU vectors to the interrupt routine. When IT1 is cleared, IE1 is sampled and inverted from the
external interrupt pin. The flag will be set or cleared by hardware depending on the state of P3.3.
Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
Interrupt 0 flag. When IT0 is set, IE0 is set by hardware when the external interrupt falling edge is detected, and is cleared
by hardware when the CPU vectors to the interrupt routine. When IT0 is cleared, IE0 is sampled and inverted from the
external interrupt pin. The flag will be set or cleared by hardware depending on the state of P3.2.
Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
7
TCON
– Timer/Counter Control Register
TR1
6
TF0
5
TR0
4
IE1
3
IT1
2
AT89LP2052/LP4052
Reset Value = 0000 0000B
IE0
1
IT0
0
27

Related parts for AT89LP2052