AT89S2051 Atmel Corporation, AT89S2051 Datasheet - Page 18

• Manufacturer Part Number: AT89S2051
• Manufacturer: Atmel Corporation

Specifications of AT89S2051

• Flash (kbytes): 2 Kbytes
• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 15
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 2
• Isp: SPI

18. Analog Comparator
19. Comparator Interrupt with Debouncing
18
AT89S2051/S4051
A single analog comparator is provided in the AT89S2051/S4051. The comparator operation is
such that the output is a logical “1” when the positive input AIN0 (P1.0]) is greater than the neg-
ative input AIN1 (P1.1). Otherwise the output is a zero. Setting the CEN bit in ACSR enables the
comparator. When the comparator is first enabled, the comparator output and interrupt flag are
not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt
should not be enabled during that time, and the comparator interrupt flag must be cleared before
the interrupt is enabled in order to prevent an immediate interrupt service.
The comparator may be configured to cause an interrupt under a variety of output value condi-
tions by setting the CM bits in ACSR. The comparator interrupt flag CF in ACSR is set whenever
the comparator output matches the condition specified by CM. The flag may be polled by soft-
ware or may be used to generate an interrupt and must be cleared by software. The analog
comparator is always disabled during Idle or Power-down modes.
The comparator output is sampled at every State 4 (S4) of every machine cycle. The conditions
on the analog inputs may be such that the comparator output will toggle excessively. This is
especially true if applying slow moving analog inputs. Three debouncing modes are provided to
filter out this noise. In debouncing mode, the comparator uses Timer 1 to modulate its sampling
time. When a relevant transition occurs, the comparator waits until two Timer 1 overflows have
occurred before resampling the output. If the new sample agrees with the expected value, CF is
set. Otherwise, the event is ignored. The filter may be tuned by adjusting the timeout period of
Timer 1. Because Timer 1 is free running, the debouncer must wait for two overflows to guaran-
tee that the sampling delay is at least 1 timeout period. Therefore after the initial edge event, the
interrupt may occur between 1 and 2 timeout periods later. See
Figure 19-1. Example of Negative Edge Comparator Interrupt with Debouncing
Timer 1 Overflow
Comparator Out
CF
START
COMPARE
START
Figure
COMPARE
19-1.
3390E–MICRO–6/08