AT89S2051 Atmel Corporation, AT89S2051 Datasheet - Page 7
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AT89S2051
Manufacturer Part Number
AT89S2051
Description
Manufacturer
Atmel Corporation
Specifications of AT89S2051
Flash (kbytes)
2 Kbytes
Max. Operating Frequency
24 MHz
Cpu
8051-12C
Max I/o Pins
15
Uart
1
Sram (kbytes)
0.25
Operating Voltage (vcc)
2.7 to 5.5
Timers
2
Isp
SPI
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8. Restrictions on Certain Instructions
8.1
8.2
9. Program Memory Lock Bits
3390E–MICRO–6/08
Branching Instructions
MOVX-related Instructions, Data Memory
The AT89S2051/S4051 is an economical and cost-effective member of Atmel’s family of micro-
controllers. It contains 2K/4K bytes of Flash program memory. It is fully compatible with the
MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However,
there are a few considerations one must keep in mind when utilizing certain instructions to pro-
gram this device.
All the instructions related to jumping or branching should be restricted such that the destination
address falls within the physical program memory space of the device, which is 2K/4K for the
AT89S2051/S4051. This should be the responsibility of the software programmer. For example,
LJMP 7E0H would be a valid instruction for the AT89S2051 (with 2K of memory), whereas LJMP
900H would not.
LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR. These unconditional branching
instructions will execute correctly as long as the programmer keeps in mind that the destination
branching address must fall within the physical boundaries of the program memory size (loca-
tions 00H to 7FFH/FFFH for the AT89S2051/S4051). Violating the physical space limits may
cause unknown program behavior.
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ. With these conditional branching
instructions, the same rule above applies. Again, violating the memory boundaries may cause
erratic execution.
For applications involving interrupts, the normal interrupt service routine address locations of the
80C51 family architecture have been preserved.
The AT89S2051/S4051 contains 256 bytes of internal data memory. External DATA memory
access is not supported in this device, nor is external PROGRAM memory execution. Therefore,
no MOVX [...] instructions should be included in the program.
A typical 80C51 assembler will still assemble instructions, even if they are written in violation of
the restrictions mentioned above. It is the responsibility of the user to know the physical features
and limitations of the device being used and adjust the instructions used accordingly.
On the chip are two lock bits which can be left unprogrammed (U) or can be programmed (P) to
obtain the additional features listed in
Table 9-1.
Note:
1
2
3
1. The Lock Bits can only be erased with the Chip Erase operation.
Program Lock Bits
Lock Bit Protection Modes
LB1
U
P
P
LB2
U
U
P
Table
(1)
Protection Type
No program lock features.
Further programming of the Flash is disabled.
Same as mode 2, also verify is disabled.
9-1:
AT89S2051/S4051
7