AT90CAN64 Automotive Atmel Corporation, AT90CAN64 Automotive Datasheet - Page 120
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AT90CAN64 Automotive
Manufacturer Part Number
AT90CAN64 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(431 pages)
2.AT90CAN128_AUTOMOTIVE.pdf
(16 pages)
3.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
Specifications of AT90CAN64 Automotive
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- AT90CAN128_AUTOMOTIVE PDF datasheet #2
- AT90CAN128_AUTOMOTIVE PDF datasheet #3
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13.5
120
Counter Unit
AT90CAN32/64/128
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 13-2
Figure 13-2. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con-
taining the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight
bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNTnH value when the TCNTnL is read, and
TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNTn Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the
timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of
whether clk
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OCnx. For more details about advanced counting
sequences and waveform generation, see
Count
Direction
Clear
clk
TOP
BOTTOM
T
n
T
shows a block diagram of the counter and its surroundings.
n
TCNTnH (8-bit)
TEMP (8-bit)
is present or not. A CPU write overrides (has priority over) all counter clear or
TCNTn (16-bit Counter)
DATA BUS
T
n
). The clk
TCNTnL (8-bit)
Increment or decrement TCNTn by 1.
Select between increment and decrement.
Clear TCNTn (set all bits to zero).
Timer/Counter clock.
Signalize that TCNTn has reached maximum value.
Signalize that TCNTn has reached minimum value (zero).
(8-bit)
T
n
can be generated from an external or internal clock source,
“Modes of Operation” on page
Direction
Count
Clear
Control Logic
TOP
BOTTOM
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
126.
Detector
Edge
7682C–AUTO–04/08
Tn
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