ATmega1280 Atmel Corporation, ATmega1280 Datasheet - Page 167

• Manufacturer Part Number: ATmega1280
• Manufacturer: Atmel Corporation

Specifications of ATmega1280

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 86
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 16
• Input Capture Channels: 4
• Pwm Channels: 15
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.11.37 TIFR1 – Timer/Counter1 Interrupt Flag Register
17.11.38 TIFR3 – Timer/Counter3 Interrupt Flag Register
17.11.39 TIFR4 – Timer/Counter4 Interrupt Flag Register
17.11.40 TIFR5 – Timer/Counter5 Interrupt Flag Register
2549N–AVR–05/11
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(see
• Bit 5 – ICFn: Timer/Countern, Input Capture Flag
This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register
(ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn Flag is set when the coun-
ter reaches the TOP value.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICFn can be cleared by writing a logic one to its bit location.
• Bit 3– OCFnC: Timer/Countern, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register C (OCRnC).
Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC Flag.
OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is exe-
cuted. Alternatively, OCFnC can be cleared by writing a logic one to its bit location.
Bit
0x16 (0x36)
Read/Write
Initial Value
Bit
0x18 (0x38)
Read/Write
Initial Value
Bit
0x19 (0x39)
Read/Write
Initial Value
Bit
0x1A (0x3A)
Read/Write
Initial Value
“Interrupts” on page
R
R
R
R
7
–
0
7
–
0
7
–
0
7
–
0
“Interrupts” on page
105) is executed when the TOVn Flag, located in TIFRn, is set.
R
R
R
R
6
–
0
6
–
0
6
–
0
6
–
0
ATmega640/1280/1281/2560/2561
ICF1
ICF3
ICF4
ICF5
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
105) is executed when the OCFnA Flag, located in
R
R
R
R
4
–
0
4
–
0
4
–
0
4
–
0
OCF1C
OCF3C
OCF4C
OCF5C
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
OCF1B
OCF3B
OCF4B
OCF5B
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
OCF1A
OCF3A
OCF4A
OCF5A
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
TOV1
TOV3
TOV4
TOV5
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TIFR1
TIFR3
TIFR4
TIFR5
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