ATmega329 Atmel Corporation, ATmega329 Datasheet - Page 45
ATmega329
Manufacturer Part Number
ATmega329
Description
Manufacturer
Atmel Corporation
Specifications of ATmega329
Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.8
2552K–AVR–04/11
Watchdog Timer
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at V
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in
dog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega329/3290/649/6490 resets and
executes from the Reset Vector. For timing details on the Watchdog Reset, refer to
on page
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in Table 10-1. Refer to
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 47
details.
Table 10-1.
Figure 10-7. Watchdog Timer
WDTON
Unprogrammed
Programmed
46.
Table 10-2 on page
WDT Configuration as a Function of the Fuse Settings of WDTON
Safety
Level
CC
1
2
= 5V. See characterization data for typical values at other V
OSCILLATOR
WATCHDOG
WDT Initial
State
Disabled
Enabled
46. The WDR – Watchdog Reset – instruction resets the Watch-
ATmega329/3290/649/6490
How to Disable the
WDT
Timed sequence
Always enabled
How to Change
Time-out
Timed sequence
Timed sequence
CC
Table 10-2
levels. By
for
45
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