ATmega3290 Atmel Corporation, ATmega3290 Datasheet - Page 104

• Manufacturer Part Number: ATmega3290
• Manufacturer: Atmel Corporation

Specifications of ATmega3290

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

104
ATmega329/3290/649/6490
Table 14-2.
Note:
• Bit 5:4 – COM0A1:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting.
are set to a normal or CTC mode (non-PWM).
Table 14-3.
Table 14-4
mode.
Table 14-4.
Note:
Table 14-5
rect PWM mode.
Mode
COM0A1
COM0A1
0
1
2
3
0
0
1
1
0
0
1
1
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
WGM01
(CTC0)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
pare match is ignored, but the set or clear is done at BOTTOM. See
page 98
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor-
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
0
0
1
1
Waveform Generation Mode Bit Description
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
COM0A0
COM0A0
0
1
0
1
0
1
0
1
for more details.
WGM00
(PWM0)
Table 14-3
0
1
0
1
Description
Normal port operation, OC0A disconnected.
Toggle OC0A on compare match
Clear OC0A on compare match
Set OC0A on compare match
Description
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match, set OC0A at BOTTOM,
(non-inverting mode)
Set OC0A on compare match, clear OC0A at BOTTOM,
(inverting mode)
Timer/Counter
Mode of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
shows the COM0A1:0 bit functionality when the WGM01:0 bits
TOP
0xFF
0xFF
OCR0A
0xFF
(1)
(1)
Update of
OCR0A at
Immediate
TOP
Immediate
BOTTOM
TOV0 Flag
Set on
MAX
BOTTOM
MAX
MAX
“Fast PWM Mode” on
2552K–AVR–04/11