ATmega8A Atmel Corporation, ATmega8A Datasheet - Page 220

• Manufacturer Part Number: ATmega8A
• Manufacturer: Atmel Corporation

Specifications of ATmega8A

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.8.8
23.8.9
23.8.10
8159D–AVR–02/11
EEPROM Write Prevents Writing to SPMCR
Reading the Fuse and Lock Bits from Software
Preventing Flash Corruption
It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock Bits. When
programming the Lock Bits the entire Flash can be read during the operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock Bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCR Register.
It is possible to read both the Fuse and Lock Bits from software. To read the Lock Bits, load the
Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruc-
tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCR,
the value of the Lock Bits will be loaded in the destination register. The BLBSET and SPMEN
bits will auto-clear upon completion of reading the Lock Bits or if no LPM instruction is executed
within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-
SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low bits is similar to the one described above for reading the
Lock Bits. To read the Fuse Low bits, load the Z-pointer with 0x0000 and set the BLBSET and
SPMEN bits in SPMCR. When an LPM instruction is executed within three cycles after the BLB-
SET and SPMEN bits are set in the SPMCR, the value of the Fuse Low bits (FLB) will be loaded
in the destination register as shown below. Refer to
description and mapping of the fuse low bits.
Similarly, when reading the Fuse High bits, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR,
the value of the Fuse High bits (FHB) will be loaded in the destination register as shown below.
Refer to
Fuse and Lock Bits that are programmed, will be read as zero. Fuse and Lock Bits that are
unprogrammed, will be read as one.
During periods of low V
low for the CPU and the Flash to operate properly. These issues are the same as for board level
systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
Bit
Rd
Bit
Rd
Bit
Rd
Table 24-3 on page 227
FLB7
FHB7
7
–
7
7
CC,
FHB6
FLB6
6
–
6
6
the Flash program can be corrupted because the supply voltage is too
BLB12
for detailed description and mapping of the fuse high bits.
FHB5
FLB5
5
5
5
BLB11
FLB4
FHB4
4
4
4
BLB02
FLB3
FHB3
3
3
3
Table 24-4 on page 228
BLB01
FHB2
FLB2
2
2
2
FLB1
FHB1
LB2
1
1
1
ATmega8A
FLB0
FHB0
LB1
0
0
0
for a detailed
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